mattkretz / wg21-papers

my papers to WG21 — the C++ committee
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improve "target/architecture" wording #48

Closed mattkretz closed 7 years ago

mattkretz commented 7 years ago
mattkretz commented 7 years ago

On the 3rd point: After reviewing the AMD Zen architecture a bit, it seems "most efficient data parallel execution for the element type T" means 16-Byte vectors for Zen, even though the ISA supports AVX2. Ultimately, this is up to the implementation, but the intent of the wording is not to require the widest usable vector register size.

mattkretz commented 7 years ago

I added several margin notes with alternative text avoiding "target architecture" and "target system" in normative wording. Better?