bigspicy is a tool for merging circuit descriptions (netlists), generating Spice decks modeling those circuits, generating Spice tests to measure those models, and analyzing the results of running Spice on those tests.
bigspicy allows you to combine structural Verilog from a PDK, Spice models of standard cells, a structural Verilog model of some circuit implemented in that PDK, and parasitics extracted into SPEF format. You can then reason about the electrical structure of the design however you want.
bigspicy generates Spice decks in Xyce format, though this can (and should) be extended to other Spice dialects. (That is why we recommend setting up Xyce below.)
mithro
commented
2 years ago
It would be awesome to do analog simulation of the complete circuit with the adder included!
Maybe https://github.com/google/bigspicy could help here?