add sram block

[mattvenn]

we are documenting progress/ideas here https://docs.google.com/document/d/1-8AeNIIzsXWtidUxx8xsDvId14Mii2BdkWXOwrHh3jc/edit#

@embelon is working on this.

[mattvenn]

• install sram instructions: export SRAM_INSTALL=yes ; make pdk
• add sram instantce to uprj_netlist
• add sram to macro
• add block layer around sram macro
• instantiate and connect the sram in user_project_wrapper - needs extra wires
• add openram port to the shim instance
• how to harden after, still getting 3M drc with openram inside

[mattvenn]

still needs to be accessible to the other projects.

we already have the openram definition in projects.yaml->interfaces

also missing from wrapper.v template. Update for MPW4 need to add this.

Then the wires need to be connected:

• disconnect wb shim from picorv32 wishbone
• if a project specifies 'openram' interface, then wire it up

[mattvenn]

Matt's suggestion

pros: simple cons: caravel can't write to ram, so user project would have to provide an arbiter

frame buffer example

[mattvenn]

Pawel's suggestion:

pros: caravel can write directly to sram, reduces complexity from user projects, sram can be used as a shared memory cons: more complex

• arbiter needed in the case that caravel is writing to openram and an active user project responds to the same address
• dual port shim:
  • translates wishbone to the openram native interface
  • control signal can swap the channels, so the RO port is connected to either caravel or the user project

[mattvenn]

qs from Urish

1. What does the address space for the SRAM WB bus look like?

   • from caravel, upper 1 k. we can do what we want. this address will be set in the shim (see pic above)

2. What's the width of the SRAM data / address wires? (SRAM 1k is organised 32x256)

   • 32 bit data,
   • 8 bit address

3. What's the minimum write width?

   • we have a mask, so can write 1 byte

other qs

1. how long does it take to read and write
   • read is 2 cycles, write 2 cycles (maybe 3 - we need to check)

[mattvenn]

left to be done for MPW4

• Pawel finish dual port shim and test it
• Pawel to do the arbiter mux and test it
• Matt to document the design
• Matt to provide an example pattern generator
  • wishbone registers for period (cycles), starting address
  • wishbone register for start/stop
  • reads 4x8 bit values from memory and puts them one at a time on the gpio
  • and provide a testbench with caravel firmware
• Matt to update multi_project_tools to instantiate the mux and wire the 2nd RAMBus

left to be done for future

• clock domain crossing. At the moment the designs would need to use the same clock as caravel management

[urish]

from caravel, upper 1 k. we can do what we want. this address will be set in the shim (see pic above)

From our projects too?

edit: nvm, I see the address bus is 8-bit wide, so the ram occupies the entire address space