this PR changes the way that multi project tools handles interfaces.
Features
interfaces are now defined in projects.yaml. Also moved some configuration in there
entire code generation has been moved into codegen/
allocator.py provides a pluggable way to change the allocation, currently the legacy method has been implemented
in future this will be expanded to read/write files for the PBIL generator
caravel_codegen.py now contains the entire verilog-generating code. Caravel iface has been moved to this catalog as well
Testing
pull repos
run using ./multi_tool.py --copy-gds --create-openlane-config --fill 16 --force-delete
go to caravel project, make user_project_wrapper
this will most likely fail saying wrapped_frequency_counter' referenced in moduleuser_project_wrapper' in cell `wrapped_frequency_counter_15' does not have a port named 'vssd1'.
this is because the macros we are using have ifdefs that disable power. For now manually go to mpw3_repos and edit wrapper.v files to always include vccd1 and vssd1. repeat 2 + 3
inspect generated files
macros:
includes:
wrapper:
hardened design can be inspected by klayout openlane/user_project_wrapper/runs/user_project_wrapper/results/routing/23-user_project_wrapper.def
this PR changes the way that multi project tools handles interfaces.
Features
Testing
./multi_tool.py --copy-gds --create-openlane-config --fill 16 --force-delete
wrapped_frequency_counter' referenced in module
user_project_wrapper' in cell `wrapped_frequency_counter_15' does not have a port named 'vssd1'.this is because the macros we are using have ifdefs that disable power. For now manually go to mpw3_repos and edit wrapper.v files to always include vccd1 and vssd1. repeat 2 + 3
inspect generated files macros:
includes:
wrapper:
hardened design can be inspected by klayout openlane/user_project_wrapper/runs/user_project_wrapper/results/routing/23-user_project_wrapper.def