Closed myklemykle closed 1 year ago
BTW if there's any good example of a boot_stage2 file written to support QSPI without Continuous Read, please point me at it. Thanks.
I've never written one of these flash definitions myself, they all come from https://github.com/adafruit/nvm.toml/tree/main. Please check out if your chip is already there with the specifications you need and it not, open an issue there. Pulling updated definitions into here is easy and the .S
files can be generated then.
Hi, I'm trying to figure out QPSI support for the 1.8v Winbond W25Q128JW flash chip. I picked this chip thinking it had the same command set/API as the already-supported 3.3v W25Q128JV chip, but I was wrong. Comparing the datasheets more closely now, the most significant difference I see is that the 1.8v JW chip, while supporting QSPI and Fast Read Quad Output, does not support the Continuous Read mode where subsequent reads don't need to issue a command prefix.
Maybe it would be "relatively straightforward" to create a boot_stage2.c file for this chip? Would the SSI just need to be told to issue the 0x6b command prefix for every read? I've been trying to find some example to start modifying in that direction ... however, all of the boot_stage2 examples I can find presume that continuous read mode is present. The file "stage2.c.jinja" in this repo seems to assume that if QSPI is present (if that's what "quad_ok" means), then Continuous Read is also present, so there's a great deal of code & assumptions there that it looks like I would have to remove.
I could be wrong about this, but comparing the datasheets of the 1.8v JW with the 3.3v JV, continuous mode seems to be the big difference. The continuous mode bits M7-M0 are documented for the JV, but the JW just calls those a dummy byte.
https://www.winbond.com/resource-files/W25Q128JW_RevG_07292021%20Plus.pdf
Meanwhile, I don't seen any flag in the nvm.template.toml to specify whether Continuous Read is supported. In general, this whole codebase seems to believe that all chips which support QSPI support Continuous Read. Am I wrong about that? Is there any plan to support flash chips where that isn't true?