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mayurkubavat / SystemVerilog

SystemVerilog examples and projects
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No design files #1

Open kautilyakukunoor opened 7 years ago

kautilyakukunoor commented 7 years ago

We need design files to write a testbench but there is a code for testbench and no design files

mayurkubavat commented 7 years ago

For what particular code are you asking about? AHB/APB are VIPs, so there's no design but SV code connected back to back. Search on verification IP for more. Only AHB-APB bridge does not have RTL with it.