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mazegen / x86reference

X86 Opcode and Instruction Reference
https://ref.x86asm.net
GNU Lesser General Public License v3.0
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Add "system" instructions and prefixes #12

Open mazegen opened 4 months ago

mazegen commented 4 months ago

Add "system" instructions and prefixes

INVPCID     Invalidate Process-Context Identifier (ring 0)
PREFETCHW   Prefetch Data into Caches in Anticipation of a Write (note: all flags are affected)
PREFETCHWT1 Prefetch Vector Data Into Caches with Intent to Write and T1 Hint (note: all flags are affected)
RDFSBASE    Read FS Segment Base
RDGSBASE    Read GS Segment Base
WRFSBASE    Write FS Segment Base
WRGSBASE    Write GS Segment Base
RDRAND      Read Random Number (note: all flags are affected)
RDSEED      Read Random SEED (note: all flags are affected)
XACQUIRE    Hardware Lock Elision Prefix Hint
XRELEASE    Hardware Lock Elision Prefix Hint
XRSTORS     Restore Processor Extended States Supervisor (ring 0)
XRSTORS64
XSAVEC      Save Processor Extended States with Compaction
XSAVEC64
XSAVEOPT    Save Processor Extended States Optimized
XSAVEOPT64
XSAVES      Save Processor Extended States Supervisor
XSAVES64

HLE/RTM:

XBEGIN  Transactional Begin
XABORT  Transactional Abort
XEND    Transactional End

NP 0F 01 D6 XTEST   Test if in Transactional Execution

OSPKE:

RDPKRU  Read Protection Key Rights for User Pages
WRPKRU  Write Data to User Page Key Register

SGX1:

ENCLS   Execute an Enclave System Function of Specified Leaf Number
ENCLU   Execute an Enclave User Function of Specified Leaf Number
mazegen commented 4 months ago

Also:

0F FF /r UD0 r32, r/m32
mazegen commented 4 months ago

Also:

F3 0F 3A F0 C0 /ib HRESET imm8, <EAX>   History Reset
mazegen commented 4 months ago

Also:

F3 0F 1E FB ENDBR32   Terminate an Indirect Branch in 32-bit and Compatibility Mode
F3 0F 1E FA ENDBR64   Terminate an Indirect Branch in 64-bit Mode

F2 0F 38 F8 ENQCMD r32/r64, m512    Enqueue Command
F3 0F 38 F8 ENQCMDS r32/r64, m512   Enqueue Command Supervisor
mazegen commented 4 months ago 
F3 0F AE /4 PTWRITE r32/m32   Write Data to a Processor Trace Packet
F3 REX.W 0F AE /4 PTWRITE r64/m64

F3 0F C7 /7 RDPID r32   Read Processor ID
F3 0F C7 /7 RDPID r64   Read Processor ID

NP 0F 01 E8 SERIALIZE   Serialize Instruction Execution

F3 0F 01 EF STUI   Set User Interrupt Flag
F3 0F 01 ED TESTUI   Determine User Interrupt Flag
F3 0F 01 EC UIRET   User-Interrupt Return
F3 0F C7 /6 SENDUIPI reg   Send User Interprocessor Interrupt

66 0F AE /6 TPAUSE r32, <edx>, <eax>   Timed PAUSE

F3 0F AE /6 UMONITOR r16/r32/r64   User Level Set Up Monitor Address
F2 0F AE /6 UMWAIT r32, <edx>, <eax>   User Level Monitor Wait

F3 0F 09 WBNOINVD   Write Back and Do Not Invalidate Cache

F2 0F 01 E8 XSUSLDTRK   Suspend Tracking Load Addresses
F2 0F 01 E9 XRESLDTRK   Resume Tracking Load Addresses

NP 0F 01 C5 PCONFIG   Platform Configuration