Feature request: Support custom hex format

[nikhenri]

Hi, I am a FPGA designer and I found your extensions very useful. The problem is when I m writing HEX in SytemVerilog, I don't use 0x prefix so the extension doesn't work

This is how a HEX is done in SystemVerilog

Do you think it would be possible to add the support of this prefix ? Thank you

[maziac]

Is the prefix a sole h or is it a 'h ?

[nikhenri]

' give the base, so the 'h is the whole prefix.

I don't know your level of motivation, but there is also the 'b that is a prefix for binary string, ex: a<= 'b1010

Here a document explaining the format in details: http://web.engr.oregonstate.edu/~traylor/ece474/beamer_lectures/verilog_number_literals.pdf

[maziac]

Could you please try this version: https://github.com/maziac/hex-hover-converter/releases/tag/v1.2.0 It should allow decoding verily hex and binary numbers. (But not decimal format)

[nikhenri]

Hex seem to work correctly, with or without size

The binary is seen as hex, with or without size expected: Dec: 4, Hex: 4 I think it's a display bug

Dont worry about 'd since if you don't write prefix, it's treaded as decimal 'd9 == 9

[maziac]

Could you please try https://github.com/maziac/hex-hover-converter/releases/tag/v1.2.1

d should be supported and for b it should not display the hex anymore.

[nikhenri]

Work perfectly! Thank you