Use of SVAUnit for assertions verification

[muneebullashariff]

Checking the checkers

https://github.com/amiq-consulting/svaunit/blob/master/docs/SystemVerilog_Assertions_Verification_with_SVAUnit_paper.doc

https://www.amiq.com/consulting/wp-content/themes/Amiq-Unify/papers/SVAUnit/AMIQ_SVAUnit_SNUG_2015.pdf

https://github.com/amiq-consulting/svaunit

https://github.com/amiq-consulting/svaunit/blob/master/docs/SVAUnitUserGuide.pdf

https://blog.verificationgentleman.com/2016/07/24/a-quick-look-at-svaunit.html

https://www.accellera.org/resources/videos/systemverilog-assertions-tutorial-2016

https://www.accellera.org/images/resources/videos/SystemVerilog_Assertions_Tutorial_2016.pdf

https://www.amiq.com/consulting/2017/02/20/svaunit-3-2-release-is-available/

Use SVAUnit for assertions a. This is important as the assertions need to be verified We can even have randomized way of testing the assertions

[muneebullashariff]

• Can use #83 to create the digital waveforms to convert a requirement to waveform, then we can add assertions to meet the requirements.
• This will make development of assertions easier and maintainable. That is, every-time the digital waveform changes, then we need update the assertions accordingly. good way to track it down.

[muneebullashariff]

Examples of SVAUnit: https://www.edaplayground.com/playgrounds?searchString=&language=&simulator=&methodologies=&libraries=SVAUnit&_libraries=on&_svx=on&_easierUVM=on&curated=true&_curated=on

[muneebullashariff]

https://github.com/verification-gentleman-blog/getting-started-with-sva https://github.com/verification-gentleman-blog/svaunit_sandbox