Experiments and information of -out

[Gopalsuthar2308]

Using -out option in create_unit_test.pl we can create multiple unit test template for single UUT.

[Gopalsuthar2308]

Here I have even_odd.sv file.

Now I want to create two unit test template for this even_odd.sv class. So using -out we can create multiple unit test template with different name.

[Gopalsuthar2308]

If we don't use -out option then it will create only one unit test template with default name even_odd_unit_test.sv shown i below,

run command and output:

create_unit_test.pl even_odd.sv

Here I created even_odd_unit_test.sv. If you want you can copy paste and change name of unit test shown in below,

cp even_odd_unit_test.sv new_unit_test.sv

Also we need to change module name and string name inside this unit test.

module even_odd_unit_test;
  import svunit_pkg::svunit_testcase;

  string name = "even_odd_ut";
  svunit_testcase svunit_ut;

Here module name is even_odd_unit_test and string name is even_odd_ut.

[Gopalsuthar2308]

But if you use -out then it will create different unit test template with user name, Only we need to change module name and string name inside unit test.

run command:

1. Creating even_unit_test: create_unit_test.pl even_odd.sv -out even_unit_test.sv

2. Creating odd_unit_test: create_unit_test.pl even_odd.sv -out odd_unit_test.sv

Output:

[Gopalsuthar2308]

Here in the output two unit test created even_unit_test.sv and odd_unit_test.sv but both files module name same shown in below snippet,

even_unit_test.sv

module even_odd_unit_test;
  import svunit_pkg::svunit_testcase;

  string name = "even_odd_ut";
  svunit_testcase svunit_ut;

Click on below even_unit_test for full test template code.

even_unit_test

```systemverilog `include "svunit_defines.svh" `include "even_odd.sv" module even_odd_unit_test; import svunit_pkg::svunit_testcase; string name = "even_odd_ut"; svunit_testcase svunit_ut; //=================================== // This is the UUT that we're // running the Unit Tests on //=================================== even_odd my_even_odd; //=================================== // Build //=================================== function void build(); svunit_ut = new(name); my_even_odd = new(/* New arguments if needed */); endfunction //=================================== // Setup for running the Unit Tests //=================================== task setup(); svunit_ut.setup(); /* Place Setup Code Here */ endtask //=================================== // Here we deconstruct anything we // need after running the Unit Tests //=================================== task teardown(); svunit_ut.teardown(); /* Place Teardown Code Here */ endtask //=================================== // All tests are defined between the // SVUNIT_TESTS_BEGIN/END macros // // Each individual test must be // defined between `SVTEST(_NAME_) // `SVTEST_END // // i.e. // `SVTEST(mytest) // // `SVTEST_END //=================================== `SVUNIT_TESTS_BEGIN `SVUNIT_TESTS_END endmodule ```

odd_unit_test.sv

module even_odd_unit_test;
  import svunit_pkg::svunit_testcase;

  string name = "even_odd_ut";
  svunit_testcase svunit_ut;

Click on below odd_unit_test for full test template code.

odd_unit_test

```systemverilog `include "svunit_defines.svh" `include "even_odd.sv" module even_odd_unit_test; import svunit_pkg::svunit_testcase; string name = "even_odd_ut"; svunit_testcase svunit_ut; //=================================== // This is the UUT that we're // running the Unit Tests on //=================================== even_odd my_even_odd; //=================================== // Build //=================================== function void build(); svunit_ut = new(name); my_even_odd = new(/* New arguments if needed */); endfunction //=================================== // Setup for running the Unit Tests //=================================== task setup(); svunit_ut.setup(); /* Place Setup Code Here */ endtask //=================================== // Here we deconstruct anything we // need after running the Unit Tests //=================================== task teardown(); svunit_ut.teardown(); /* Place Teardown Code Here */ endtask //=================================== // All tests are defined between the // SVUNIT_TESTS_BEGIN/END macros // // Each individual test must be // defined between `SVTEST(_NAME_) // `SVTEST_END // // i.e. // `SVTEST(mytest) // // `SVTEST_END //=================================== `SVUNIT_TESTS_BEGIN `SVUNIT_TESTS_END endmodule ```

In both files module name and string name is same so we need to change only module name and string name, shown in below figure before and after changing module name and string name.