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mbuesch / crcgen

Generator for CRC HDL code (VHDL, Verilog, MyHDL)
https://bues.ch/h/crcgen
GNU General Public License v2.0
29 stars 8 forks source link

corrected generation of MyHDL code: previous code would convert but not simulate #3

Closed josyb closed 1 year ago

josyb commented 1 year ago

fixes issue #2

mbuesch commented 1 year ago

Thanks a lot for your PR. But please do not do these whitespace changes.

josyb commented 1 year ago

Sorry, The formatter is always on. If you don't like the whitespace, discard the PR then. No hard feelings.

Regards, Josy