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mc-imperial
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spirv-control-flow
Formal modelling of SPIR-V control flow using Alloy
Apache License 2.0
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Add rule to model to avoid conditional branch on loop header that does not target a merge or continue
#56
afd
closed
1 year ago
3
Add a timeout for processing CFGs with Alloy
#55
Jack-Clark
closed
1 year ago
0
Update naming in test_0.xml to reflect changes to Alloy model
#54
Jack-Clark
closed
1 year ago
0
Add POPL artifact
#27
afd
closed
1 year ago
0
test_0.xml example uses old format
#26
Jack-Clark
closed
1 year ago
0
SPIRV-Cross->HLSL: undeclared identifier
#25
Jack-Clark
opened
2 years ago
0
ContinueTargetStructurallyDominatesBackEdge axiom slightly too strong?
#24
johnwickerson
closed
1 year ago
4
Barriers with multiple paths
#23
Jack-Clark
closed
2 years ago
0
MESA: validate_intrinsic_instr: Assertion `dst' failed.
#22
Jack-Clark
opened
2 years ago
0
MESA - OpPhi Vulkan CTS: Verifier failed: 0 == 20, at index 7
#21
Jack-Clark
opened
2 years ago
0
Config
#20
Jack-Clark
closed
2 years ago
0
Op phi
#19
Jack-Clark
closed
2 years ago
0
Parallel fleshing
#18
Jack-Clark
closed
2 years ago
0
'buffer' attribute parameter is out of bounds: must be between 0 and 30
#17
vili-1
closed
2 years ago
1
Order of OpSwitch Target Operands
#28
vili-1
opened
2 years ago
4
Cross compile SPIR-V from amber files into various target languages
#16
Jack-Clark
closed
2 years ago
0
Test runner
#15
Jack-Clark
closed
2 years ago
0
MESA: nir_lower_phis_to_regs_block: Assertion `src->src.is_ssa' failed.
#14
Jack-Clark
opened
2 years ago
0
MESA: Loop breaks can only break out of the inner most nested loop level
#13
Jack-Clark
opened
2 years ago
0
Vulkan: missing validation layers: VK_LAYER_LUNARG_standard_validation
#12
vili-1
opened
2 years ago
8
MESA: NIR validation failed after nir_opt_if
#11
Jack-Clark
opened
2 years ago
0
SwiftShader: Verifier failed: 0 == 8, at index 0
#10
Jack-Clark
opened
2 years ago
5
SwiftShader: Segfault
#9
Jack-Clark
opened
2 years ago
7
SwiftShader: Infinite Loop
#8
Jack-Clark
opened
2 years ago
6
MESA: SPIR-V offset 0: SPIR-V parsing FAILED: Invalid back or cross-edge in the CFG
#7
Jack-Clark
opened
2 years ago
12
Add Android support to Amber runner
#6
afd
closed
2 years ago
0
Fleshing
#5
Jack-Clark
closed
2 years ago
0
Make the Alloy validity check optional in spirv-to-alloy
#4
Jack-Clark
closed
2 years ago
0
Fleshing: Vulkan::Calling vkWaitForFences Timeout
#53
Jack-Clark
opened
2 years ago
7
Branch to continue target
#29
vili-1
opened
2 years ago
4
No error handling for alloystar subprocess
#3
Jack-Clark
closed
2 years ago
0
Add error handling to alloystar command
#2
Jack-Clark
closed
2 years ago
0
Add VulkanCTS, xml and build dirs to .gitignore
#1
Jack-Clark
closed
2 years ago
0
Fleshing Ideas
#30
Jack-Clark
opened
2 years ago
3
Post-dominance without exit blocks
#31
vili-1
opened
2 years ago
5
Structural semantics is stronger
#32
vili-1
opened
2 years ago
4
The continue target is a header block whose merge lies outside the continue construct
#33
vili-1
opened
2 years ago
2
Strange error from spirv-val about back-edges
#34
vili-1
opened
2 years ago
3
Definitions of break and continue block are problematic
#35
afd
opened
2 years ago
1
Selection must be structured
#36
vili-1
opened
2 years ago
1
OpSwitchBlockDominatesAllItsCases
#37
vili-1
opened
2 years ago
1
Pushing a set of samples at https://github.com/dneto0/spirv-samples through our tooling
#38
vili-1
opened
2 years ago
0
Discrepancy between model/spec and validator regarding OpSwitch targets
#39
afd
opened
2 years ago
0
Reachability for Reducibility
#40
vili-1
opened
2 years ago
0
(Un)structured control-flow
#41
vili-1
opened
2 years ago
2
OpSwitch: Target must be alternating scalar integer literals
#42
vili-1
opened
2 years ago
14
Incorporating structured-reachability
#43
vili-1
opened
2 years ago
0
Back-Edges
#44
vili-1
opened
2 years ago
1
Merge Block and Continue Target must be different ids
#52
vili-1
opened
2 years ago
0
HeaderBlockStrictlyDominatesItsMergeBlock
#51
vili-1
opened
2 years ago
6
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