Implement VCR registers

[mcejp]

Mainly BGCOL so that we don't have to be retarded.

[mcejp]

VS2_RTL will need to be rearchitected to draw pixel by pixel -> in RTL: split VRAM/framebuffer in memu: draw just into memory; update framebuffer by clock/2

[mcejp]

59.94 Hz refresh, 25.175 pixel clock, 50.350 cpu clock

420,000 pixel clocks / frame

[mcejp]

^ this is at 640x480, but we probably want to support multiple resolutions?

[mcejp]

1 Meg of VRAM allows 640x480x16 (614400) 320x240x24 would fit, but let's say the DAC is not that good and 16-bit color is the best that can be had

In lower-res modes, pixels and lines are simply doubled.

Configuration:

Global:

• horizontal pixel count HC (should always be 800) 10-bit
• vertical pixel count VC (should always be 525) 10-bit

Per layer:

• layer enable LE (0/1) 1bit
• pixel clock divider P (/2 ~ 640, /4 ~ 320) 1bit
• line count divider L (/1 ~ 480, /2 ~ 240) 1bit
• fetch enable FE (0/1) 1bit
• fetch period D (1, 2, 4, 8, 16) 3bit
• pointer increase N (always 2) --
• bit shift per pixel B (0, 1, 2, 4, 8) 3bit
• pixel data mask K 8bit
• line byte stride S (0..2047) 11-bit
• palette enable PE (0/1) 1-bit
• transparent color select (POST palette mapping) 16-bit

Pixel data is fetched every D pixels, always as 16-bit. Color is chosen according to palette[data & K] if PE else data & {K, 8'hFF} Every pixel, if there is no fetch, data is updated as data = data >> B If P <> 1, all this processing is only done every P-th pixel.

Examples:

• for 640x480x16: P=1, L=1, N=2, D=1, K=x, B=x, S=1280
• for 640x480x8: P=1, L=1, N=2, D=2, K=FF, B=8
• for 640x480x1: P=1, L=1, N=2, D=16, K=01, B=1
• for 320x240x8: P=2, L=2, N=2, D=2, K=FF, B=8

[mcejp]

Only 1 layer for now + BGCOL

[mcejp]

DRAM yes or no? Need to decide now. Look at HW schematics.

Proposal: NO for now, to simplify.

[mcejp]

Use SDRAM; transparent to programmer.