Open mchwang233 opened 1 year ago
import os
def do_lib(): cmd = "mkdir -p work_dut" os.system(cmd) cmd = "mkdir -p work_dut/64" os.system(cmd)
def do_rtl(): cmd = "vhdlan -vhdl93 -kdb -work WORK_DUT -f ../cfg/vhdl.f -l vhdl.log" os.system(cmd) cmd = "vlogan -f ../cfg/vlog.f -kdb -timescale=1ns/1ns -full64 -R +vc +v2k -sverilog -debug_all +define+UNIT_DELAY +lint=PCWM -work WORK_DUT -l rtl.log" os.system(cmd)
def do_tb(): cmp_cmd = "vlogan -full64 -work work -sverilog -lca -kdb +y2k -timescale=1ns/10ps -debug_access+all -f ../cfg/tb.f ${UVM_HOME}/src/dpi/uvm_dpi.cc -CFLAGS -DVCS +vcs+initreg+random" vcs_files = os.environ["verif"]+'/cfg/vcs.cfg' f=open(vcs_files) l_list = f.readlines() for vcs_cfg in l_list: vcs_cfg=vcs_cfg.replace('\n','') cmp_cmd = cmp_cmd + " " + vcs_cfg os.system(cmp_cmd+" -l tb.log")
def do_elab(): cmd = "vcs -full64 -sverilog harness -lca -kdb ${UVM_HOME}/src/dpi/uvm_dpi.cc -CFLAGS -DVCS +vcs+initreg+random -timescale=1ns/10ps -debug_access+all -partcomp +nospecify +notimingcheck -o simv -l elab.log" os.system(cmd)
def get_cmp_cmd() : rtl_files = '${RTL_HOME}/dut.f' tb_files = '../cfg/tb.f' tb_top = 'harness' vcs_files = os.environ["verif"]+'/cfg/vcs.cfg'
cmp_cmd = 'vcs -ntb_opts uvm-1.2 -full64 -sverilog -debug_all -partcomp -kdb -lca -timescale=1ps/1fs'
cmp_cmd = cmp_cmd + ' -f '+rtl_files
cmp_cmd = cmp_cmd + ' -f '+tb_files
cmp_cmd = cmp_cmd + ' -top '+ tb_top
f=open(vcs_files)
l_list = f.readlines()
for vcs_cfg in l_list:
vcs_cfg=vcs_cfg.replace('\n','')
cmp_cmd = cmp_cmd + " " + vcs_cfg
#print(cmp_cmd)
return cmp_cmd
def get_cmp_cfg() : cmp_str = ""
return cmp_str
def get_sim_cfg() : sim_str = ""
return sim_str
def get_rgs_cfg() : rgs_str = ""
return rgs_str
def get_sim_cfg(sim_cfg):
all_cfg = ''
f = open(sim_cfg)
l_list = f.readlines()
for l_cfg in l_list:
if "=" in l_cfg :
l_cfg=l_cfg.replace('\n','')
all_cfg = all_cfg+" +"+l_cfg+" "
if "simv:" in l_cfg:
l_cfg=l_cfg.replace('\n','')
l_cfg=l_cfg.replace('simv:','')
all_cfg = all_cfg+" "+l_cfg+" "
return all_cfg
import os import cmp import re import sys
is_two = 0
for part in sys.argv: if "-two" in part: is_two = 1
if is_two == 1 : cmp_cmd = cmp.get_cmp_cmd() os.system(cmp_cmd+" -l cmp.log") else : cmp.do_lib() cmp.do_rtl() cmp.do_tb() cmp.do_elab()
import re import sys import os import cmp import comm
run_cmd = '' tc_mode = '' tc_name = '' all_cfg = '' rst_cfg = '' skipc = 0 is_help = 0 is_two = 0
help_info = '''use info:
run_tc and keyword
-skipc : skip compile
tc= : tell me tc_name
mode= : which sim mode
wave= : wave name
'''
for part in sys.argv:
if "tc=" in part:
tc_name_l = re.findall("tc=(.*?)$",part)
tc_name = "".join(tc_name_l)
#print(tc_name)
if "mode=" in part:
tc_mode_l = re.findall("mode=(.*?)$",part)
tc_mode = "".join(tc_mode_l)
tc_mode = tc_mode + '/'
if "wave=" in part:
tc_wave_l = re.findall("wave=(.*?)$",part)
tc_wave = "".join(tc_wave_l)
if "-skipc" in part:
skipc = 1
if "-two" in part:
is_two = 1
if "-help" in part:
print(help_info)
skipc = 1
is_help = 1
if "cfg=" in part:
part = part.replace('cfg=','')
all_cfg = all_cfg + comm.get_sim_cfg(part)
else :
rst_cfg = rst_cfg + ' ' + part
if is_two==1 : cmp_cmd = cmp.get_cmp_cmd() run_cmd = './simv -ucli -do wave.do +fsdbfile+'+ tc_mode +tc_name +'.fsdb'+' +UVM_TESTNAME='+ tc_name + ' ' + all_cfg +' ' +rst_cfg + ' ' + '-l' + ' ' + tc_mode +tc_name + '.log'
print(run_cmd)
if skipc == 0 : if is_two == 1: os.system(cmp_cmd+" -l cmp.log") os.system(run_cmd) else: cmp.do_lib() cmp.do_rtl() cmp.do_tb() cmp.do_elab() os.system(run_cmd) else : if is_help == 0: os.system(run_cmd)
ifndef GUARD_CUST_SVT_AMBA_SYSTEM_CONFIGURATION_SV
define GUARD_CUST_SVT_AMBA_SYSTEM_CONFIGURATION_SV
class cust_svt_amba_system_configuration extends svt_amba_system_configuration;
/**
be set */
`svt_xvm_object_utils (cust_svt_amba_system_configuration)
function new (string name="cust_svt_amba_system_configuration"); super.new(name); endfunction
function void set_amba_sys_config(); /* Create two AXI, AHB and APB system envs / create_sub_cfgs(1,0,0);
this.axi_sys_cfg[0].num_masters = 0; this.axi_sys_cfg[0].num_slaves = 4;
set_axi_system_configuration(this.axi_sys_cfg[0]);
this.axi_sys_cfg[0].set_addr_range(0, 32'h7000_0000, 32'h70ff_ffff); this.axi_sys_cfg[0].set_addr_range(1, 32'h7100_0000, 32'h71ff_ffff); this.axi_sys_cfg[0].set_addr_range(2, 32'h4000_0000, 32'h40ff_ffff); this.axi_sys_cfg[0].set_addr_range(3, 32'h4000_0000, 32'h40ff_ffff);
endfunction
function void set_axi_system_configuration(svt_axi_system_configuration axi_sys_cfg);
axi_sys_cfg.create_sub_cfgs(axi_sys_cfg.num_masters, axi_sys_cfg.num_slaves); axi_sys_cfg.bus_inactivity_timeout = 0; axi_sys_cfg.system_monitor_enable = 1;
axi_sys_cfg.slave_cfg[0].addr_width = 32; axi_sys_cfg.slave_cfg[0].data_width = 128; axi_sys_cfg.slave_cfg[1].addr_width = 32; axi_sys_cfg.slave_cfg[1].data_width = 128; axi_sys_cfg.slave_cfg[2].addr_width = 32; axi_sys_cfg.slave_cfg[2].data_width = 128; axi_sys_cfg.slave_cfg[3].addr_width = 32; axi_sys_cfg.slave_cfg[3].data_width = 128;
axi_sys_cfg.common_clock_mode = 0;
axi_sys_cfg.slave_cfg[0].is_active = 1; axi_sys_cfg.slave_cfg[0].zero_delay_enable = 1; axi_sys_cfg.slave_cfg[0].axi_interface_type = svt_axi_port_configuration::AXI4; axi_sys_cfg.slave_cfg[1].is_active = 1; axi_sys_cfg.slave_cfg[1].zero_delay_enable = 1; axi_sys_cfg.slave_cfg[1].axi_interface_type = svt_axi_port_configuration::AXI4; axi_sys_cfg.slave_cfg[2].is_active = 1; axi_sys_cfg.slave_cfg[2].zero_delay_enable = 1; axi_sys_cfg.slave_cfg[2].axi_interface_type = svt_axi_port_configuration::AXI4; axi_sys_cfg.slave_cfg[3].is_active = 1; axi_sys_cfg.slave_cfg[3].zero_delay_enable = 1; axi_sys_cfg.slave_cfg[3].axi_interface_type = svt_axi_port_configuration::AXI4;
endfunction
endclass `endif // GUARD_CUST_SVT_AMBA_SYSTEM_CONFIGURATION_SV
https://wmchappy.cn/2015/07/31/jsjl-AMBA/
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