Closed jzhou1318 closed 1 month ago
We will make sure in an upcoming release, that the cases where the above happens are reported as error.
PPA.csv confusion from #3
PPA.csv Confusion
Thank you for your reply! Here is a generic answer to the understanding of why several PEs inside a tile don't change the compute latency inside HISIM:
I hope I was able to answer your question. Also, It would be better to type in your hypothesis for a behavior next time so that I can better answer your question in that regard. Leakage power will be placed as an output in the next release version.
Regarding chip_architecture, N_tier, and N_tier_real, is the logic below correct?
if chip_architect == "H2_5D" :
self.placement_method = 1
elif chip_architect == "M2D":
self.placement_method = 1
self.N_tier = 1
else:
self.placement_method = placement_method
self.N_tier = N_tier
if self.chip_architect == 'M2D' and self.N_tier_real != 1:
return "error message"
I would suggest instead to print N_tier, N_tile, N_stack and compare them with N_tier_real, N_tile_real, N_stack_real in post processing and throw an error accordingly wrt to chip architecture.
For each architecture, could you elaborate on the valid configurations of placement, N_tier_real, N_tile_real, and N_stack_real?
Opening a new issue to further discuss some issues in https://github.com/mec-UMN/HISIM/issues/3#issue-2398492680
Computing_latency (ns)
in header)2d NoC latency (ns)
,3d NoC latency (ns)
,2.5d NoC latency (ns)
in header)I've also uploaded the number PE + chip architecture combinations I'm running: extracted_PPA.csv
and the other configurations as as shown below:
hisim = HiSimModel( chip_architect = "M3D", xbar_size = 1024, N_tile = 100, N_pe = 9, N_tier = 3, freq_computing = 1, fclk_noc = 1, placement_method = 5, router_times_scale = 1, percent_router = 1, tsv_pitch = 5, W2d = 32, ai_model = 'vit', thermal = False )