medalotte / HLS-canny-edge-detection

FPGA implementation of Canny edge detection by using Vivado HLS
MIT License
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Firmware implementation #1

Open DimMichael opened 6 years ago

DimMichael commented 6 years ago

Sorry about this, I don't have any other way to contact you. I'm trying to write the firmware in SDK for the PS in a similar design based on your HLS code. I configured the DMA as SG and I am using the SDK example xaxidma_example_sg_intr.c as a base but I am unable to send/receive data from the IP.

Have you done anything similar? Also, is it possible to use it as a python overlay in Pynq Z1?

I hope you could help me.. Thank you

medalotte commented 6 years ago

Hi @DimMichael

Thank you for referring to my HLS code. Actually, I wrote this HLS code for my design that directly get image data from camera on PL. But I think data flow of your design would differ from this. Data flow of your design is like following, isn't it?

         DMA            DMA
DRAM ----------> PL ----------> DRAM

In this case, you do not need to check user signal and last signal because user signal is automatically checked, and last signal is not asserted on each end of line. Furthermore, you should set 32bit data format as input and output because of memory alignment. Probably, you can write more simply like following.

// Top Function
void improc(ap_axiu<32,1,1,1> axis_in[MAX_WIDTH*MAX_HEIGHT], ap_axiu<32,1,1,1> axis_out[MAX_WIDTH*MAX_HEIGHT]) {
    .
    .
    .
    for(int data_index = 0; data_index < MAX_WIDTH*MAX_HEIGHT; data_index++) {
        #pragma HLS PIPELINE II=1
        #pragma HLS LOOP_FLATTEN off
        fifo1[data_index] = gray(axis_in[data_index].data);
    }
    .
    .
    .
}

By the way, I use ZYBO-Z7 and refer to Digilent/Zybo-Z7-20-pcam-5c, therefore I am not familiar with python overlay in Pynq Z1.

I'm sorry I could not be helpful.