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medalotte / HLS-canny-edge-detection

FPGA implementation of Canny edge detection by using Vivado HLS
MIT License
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Modify the canny_edge_detection input stream from ImAxis<24> to ap_axiu<24,1,1,1> #2

Open 3togo opened 5 years ago

3togo commented 5 years ago

I want to modify your code so that it could take hls::stream<ap_axiu<24,1,1,1>>& instead of hls::stream<ImAxis<24>>&

i.e from void canny_edge_detection(stream<ImAxis<24>>& axis_in, stream<ImAxis<24> >& axis_out, uint8_t& hist_hthr, uint8_t& hist_lthr) to void canny_edge_detection(stream<ap_axiu<24,1,1,1>>& axis_in, stream<ap_axiu<24,1,1,1>>& axis_out, uint8_t& hist_hthr, uint8_t& hist_lthr)

But, vivado_hls keeps complaining there is left over data, can you advise me how to do it? Many thanks

3togo commented 5 years ago

not working HlsImProc.hpp.txt

medalotte commented 5 years ago

Hi @3togo

Thank you for your comment. I'm using ImAxis<24> which have only 5 signals (data, valid, ready, user, and last) instead of ap_axiu<24,1,1,1> because of due to specification of AXI VDMA.

I checked working my code using Vivado HLS 2018.2 now, however, I think it is no problem as far as I saw the synthesis log.

Could you show me such as error log?