Incorrect machine cycles for ADC A, r and BIT n, (HL)

[wsandst]

First of all, I want to thank you for making this great opcode table! It was very helpful when I was implementing the CPU for my emulator.

While developing and trying to pass memory timings tests, I noticed that a few of the machine cycle timings were off in the table, compared to the values in the pandocs (https://gbdev.io/pandocs/#instruction-set) and in https://www.pastraiser.com/.

• ADC A, r should take 1 machine cycle, not 2. (opcodes 0x88 to 0x8D and 0x8F)
• BIT n, (HL) should take 3 machine cycles, not 4. (opcodes 0xCB46, 0xCB56, 0xCB66, 0xCB76, 0xCB4E, 0xCB5E, 0xCB6E, 0xCB7E) (Note: this one is wrong in the pastraiser table as well)

I think it should just be two small changes in ADC_A_r8.js and BIT_b1_memory_at_HL.js. I could do a PR if you're alright with that?

[meganesu]

Hi there, thanks for your patience 😅 Thanks for reaching out to report this error! I think it should be fixed now. Let me know if you see any other problems (or feel free to open a PR).

Thanks again for your help!