This at least seems to be the case for the AES mode and the input and ouput fifo dma request level bits. It could be that it applies to some more bits. The intended use of the register seems to be to set the complete configuration (except for the key part) together with the enable bit.
This at least seems to be the case for the AES mode and the input and ouput fifo dma request level bits. It could be that it applies to some more bits. The intended use of the register seems to be to set the complete configuration (except for the key part) together with the enable bit.