Build and test for RISC-V

memorysafety / rav1d

An AV1 decoder in Rust.

BSD 2-Clause "Simplified" License

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Build and test for RISC-V #861

Open rinon opened 8 months ago

rinon commented 8 months ago

[ ] Add RISC-V asm (#812)
[x] Fix build on RISC-V (#775)

thedataking commented 7 months ago

[ ] Looks like the main assembly routines for RISC-V target the itx module. ~~I can easily add those in once PR #683 lands.~~ Landed.
[x] Also need to update cpumask in dav1d_cli_parse.rs.

thedataking commented 6 months ago

Currently, enabling vector support crashes qemu-riscv64-system, need to fix that. In order to enable the v target feature, QEMU needs to be invoked like this:

qemu-riscv64-static -cpu rv64,v=true,vext_spec=v1.0,vlen=256,elen=64 path/to/dav1d

Issue observed on QEMU 8.0.4. Might be worth trying on a newer release.

Notes on how to debug crashes in QEMU: https://github.com/memorysafety/rav1d/pull/227#issuecomment-1537215269