meow-chip / MeowV64

A superscalar RISC-V CPU with out-of-order execution and multi-core support
MIT License
55 stars 4 forks source link

Reduce 1 tick delay before CDB #6

Open CircuitCoder opened 4 years ago

CircuitCoder commented 4 years ago

Currently, each instruction goes through a 1 tick delay before entering the CDB. This can cause severe slowdown running code with many RAW hazards.

The 1 tick delay may be unnecessary for some functional units with less delay by its own, such as ALU, Branch and Bypass.