Only one RAM stick recognized with DDR3L

jm2 commented 4 years ago

2x8gb DDR3L; only 1x8gb shows up on both an x230 and x230t. I believe what I'm seeing is similar to this issue: https://www.reddit.com/r/coreboot/comments/amonz5/135v_ram_compatibility_and_some_research/

So it's possible this may be worked around with some simple compilation tweaks.

digmorepaka commented 4 years ago

Did you look at cbmem and seeing if there are any errors regarding memory? Do you see both spds on the smbus with i2c-tools? Did you try the sticks individually?

Regarding the reddit post, before coreboot 4.9 native ram init was very unreliable, resuming your machine from suspend was a russian roulette of sorts. That reddit post is pretty old and most of it doesn't apply anymore. Coreboot runs 1.35V ram in it's 1.5V compatibility mode, as allowed by jedec.

jm2 commented 4 years ago

I did reseat the RAM which had no effect, however considering I have two different machines with two different sets of RAM, I doubt that this is something other than a bug in the RAM detection logic.

dmidecode:

$ sudo dmidecode -t memory
# dmidecode 3.2
Getting SMBIOS data from sysfs.
SMBIOS 2.8 present.

Handle 0x000A, DMI type 17, 40 bytes
Memory Device
    Array Handle: 0x0000
    Error Information Handle: Not Provided
    Total Width: 64 bits
    Data Width: 64 bits
    Size: 8192 MB
    Form Factor: SODIMM
    Set: None
    Locator: Channel-0-DIMM-0
    Bank Locator: BANK 0
    Type: DDR3
    Type Detail: Synchronous
    Speed: 800 MT/s
    Manufacturer: Unknown (9b0d)
    Serial Number: ffffffff
    Asset Tag: Not Specified
    Part Number: None
    Rank: 2
    Configured Memory Speed: 800 MT/s
    Minimum Voltage: Unknown
    Maximum Voltage: Unknown
    Configured Voltage: Unknown

i2c-tools:

$ decode-dimms
# decode-dimms version $Revision$

Memory Serial Presence Detect Decoder
By Philip Edelbrock, Christian Zuckschwerdt, Burkart Lingner,
Jean Delvare, Trent Piepho and others

Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/0-0050
Guessing DIMM is in                              bank 1

---=== SPD EEPROM Information ===---
EEPROM CRC of bytes 0-116                        OK (0xB729)
# of bytes written to SDRAM EEPROM               176
Total number of bytes in EEPROM                  256
Fundamental Memory type                          DDR3 SDRAM
Module Type                                      SO-DIMM

---=== Memory Characteristics ===---
Maximum module speed                             1600 MHz (PC3-12800)
Size                                             8192 MB
Banks x Rows x Columns x Bits                    8 x 16 x 10 x 64
Ranks                                            2
SDRAM Device Width                               8 bits
Bus Width Extension                              0 bits
tCL-tRCD-tRP-tRAS                                11-11-11-28
Supported CAS Latencies (tCL)                    11T, 10T, 9T, 8T, 7T, 6T, 5T

---=== Timings at Standard Speeds ===---
tCL-tRCD-tRP-tRAS as DDR3-1600                   11-11-11-28
tCL-tRCD-tRP-tRAS as DDR3-1333                   10-10-10-24
tCL-tRCD-tRP-tRAS as DDR3-1066                   8-8-8-19
tCL-tRCD-tRP-tRAS as DDR3-800                    6-6-6-14

---=== Timing Parameters ===---
Minimum Cycle Time (tCK)                         1.250 ns
Minimum CAS Latency Time (tAA)                   13.750 ns
Minimum Write Recovery time (tWR)                15.000 ns
Minimum RAS# to CAS# Delay (tRCD)                13.750 ns
Minimum Row Active to Row Active Delay (tRRD)    6.000 ns
Minimum Row Precharge Delay (tRP)                13.750 ns
Minimum Active to Precharge Delay (tRAS)         35.000 ns
Minimum Active to Auto-Refresh Delay (tRC)       48.750 ns
Minimum Recovery Delay (tRFC)                    260.000 ns
Minimum Write to Read CMD Delay (tWTR)           7.500 ns
Minimum Read to Pre-charge CMD Delay (tRTP)      7.500 ns
Minimum Four Activate Window Delay (tFAW)        30.000 ns

---=== Optional Features ===---
Operable voltages                                1.5V, 1.35V
RZQ/6 supported?                                 Yes
RZQ/7 supported?                                 Yes
DLL-Off Mode supported?                          Yes
Operating temperature range                      0-95 degrees C
Refresh Rate in extended temp range              2X
Auto Self-Refresh?                               Yes
On-Die Thermal Sensor readout?                   No
Partial Array Self-Refresh?                      No
Module Thermal Sensor                            No
SDRAM Device Type                                Standard Monolithic

---=== Physical Characteristics ===---
Module Height                                    30 mm
Module Thickness                                 2 mm front, 2 mm back
Module Width                                     67.6 mm
Module Reference Card                            F revision 0
Rank 1 Mapping                                   Standard

---=== Manufacturer Data ===---
Module Manufacturer                              Unknown
DRAM Manufacturer                                Micron Technology
Manufacturing Location Code                      0x01
Manufacturing Date                               2012-W28
Part Number                                      Undefined

Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/0-0051
Guessing DIMM is in                              bank 2

---=== SPD EEPROM Information ===---
EEPROM CRC of bytes 0-116                        OK (0xB729)
# of bytes written to SDRAM EEPROM               176
Total number of bytes in EEPROM                  256
Fundamental Memory type                          DDR3 SDRAM
Module Type                                      SO-DIMM

---=== Memory Characteristics ===---
Maximum module speed                             1600 MHz (PC3-12800)
Size                                             8192 MB
Banks x Rows x Columns x Bits                    8 x 16 x 10 x 64
Ranks                                            2
SDRAM Device Width                               8 bits
Bus Width Extension                              0 bits
tCL-tRCD-tRP-tRAS                                11-11-11-28
Supported CAS Latencies (tCL)                    11T, 10T, 9T, 8T, 7T, 6T, 5T

---=== Timings at Standard Speeds ===---
tCL-tRCD-tRP-tRAS as DDR3-1600                   11-11-11-28
tCL-tRCD-tRP-tRAS as DDR3-1333                   10-10-10-24
tCL-tRCD-tRP-tRAS as DDR3-1066                   8-8-8-19
tCL-tRCD-tRP-tRAS as DDR3-800                    6-6-6-14

---=== Timing Parameters ===---
Minimum Cycle Time (tCK)                         1.250 ns
Minimum CAS Latency Time (tAA)                   13.750 ns
Minimum Write Recovery time (tWR)                15.000 ns
Minimum RAS# to CAS# Delay (tRCD)                13.750 ns
Minimum Row Active to Row Active Delay (tRRD)    6.000 ns
Minimum Row Precharge Delay (tRP)                13.750 ns
Minimum Active to Precharge Delay (tRAS)         35.000 ns
Minimum Active to Auto-Refresh Delay (tRC)       48.750 ns
Minimum Recovery Delay (tRFC)                    260.000 ns
Minimum Write to Read CMD Delay (tWTR)           7.500 ns
Minimum Read to Pre-charge CMD Delay (tRTP)      7.500 ns
Minimum Four Activate Window Delay (tFAW)        30.000 ns

---=== Optional Features ===---
Operable voltages                                1.5V, 1.35V
RZQ/6 supported?                                 Yes
RZQ/7 supported?                                 Yes
DLL-Off Mode supported?                          Yes
Operating temperature range                      0-95 degrees C
Refresh Rate in extended temp range              2X
Auto Self-Refresh?                               Yes
On-Die Thermal Sensor readout?                   No
Partial Array Self-Refresh?                      No
Module Thermal Sensor                            No
SDRAM Device Type                                Standard Monolithic

---=== Physical Characteristics ===---
Module Height                                    30 mm
Module Thickness                                 2 mm front, 2 mm back
Module Width                                     67.6 mm
Module Reference Card                            F revision 0
Rank 1 Mapping                                   Standard

---=== Manufacturer Data ===---
Module Manufacturer                              Unknown
DRAM Manufacturer                                Micron Technology
Manufacturing Location Code                      0x01
Manufacturing Date                               2012-W28
Part Number                                      Undefined

Number of SDRAM DIMMs detected and decoded: 2

cbmem logs will be added as soon as I compile the binary to read them.

jm2 commented 4 years ago

cbmem console output:

$ sudo cbmem -c

*** Pre-CBMEM romstage console overflowed, log truncated! ***
g Ivybridge RAM training (1).
100MHz reference clock support: yes
Trying CAS 11, tCK 320.
Found compatible clock, CAS pair.
Selected DRAM frequency: 800 MHz
Selected CAS latency   : 11T
PLL busy... done in 50 us
MCU frequency is set at : 800 MHz
Done dimm mapping
Update PCI-E configuration space:
PCI(0, 0, 0)[a0] = 0
PCI(0, 0, 0)[a4] = 2
PCI(0, 0, 0)[bc] = c2a00000
PCI(0, 0, 0)[a8] = 3b600000
PCI(0, 0, 0)[ac] = 2
PCI(0, 0, 0)[b8] = c0000000
PCI(0, 0, 0)[b0] = c0a00000
PCI(0, 0, 0)[b4] = c0800000
PCI(0, 0, 0)[7c] = 7f
PCI(0, 0, 0)[70] = fe000000
PCI(0, 0, 0)[74] = 1
PCI(0, 0, 0)[78] = fe000c00
Done memory map
Done io registers
t123: 1767, 6000, 7620
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : NO
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : BUP Phase
ME: Power Management Event  : Clean Moff->Mx wake
ME: Progress Phase State    : Waiting for DID BIOS message
ME: FWS2: 0x101f0126
ME:  Bist in progress: 0x0
ME:  ICC Status      : 0x3
ME:  Invoke MEBx     : 0x0
ME:  CPU replaced    : 0x0
ME:  MBP ready       : 0x1
ME:  MFS failure     : 0x0
ME:  Warm reset req  : 0x0
ME:  CPU repl valid  : 0x1
ME:  (Reserved)      : 0x0
ME:  FW update req   : 0x0
ME:  (Reserved)      : 0x0
ME:  Current state   : 0x1f
ME:  Current PM event: 0x0
ME:  Progress code   : 0x1
PASSED! Tell ME that DRAM is ready
ME: FWS2: 0x10500126
ME:  Bist in progress: 0x0
ME:  ICC Status      : 0x3
ME:  Invoke MEBx     : 0x0
ME:  CPU replaced    : 0x0
ME:  MBP ready       : 0x1
ME:  MFS failure     : 0x0
ME:  Warm reset req  : 0x0
ME:  CPU repl valid  : 0x1
ME:  (Reserved)      : 0x0
ME:  FW update req   : 0x0
ME:  (Reserved)      : 0x0
ME:  Current state   : 0x50
ME:  Current PM event: 0x0
ME:  Progress code   : 0x1
ME: Requested BIOS Action: Continue to boot
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : NO
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : BUP Phase
ME: Power Management Event  : Clean Moff->Mx wake
ME: Progress Phase State    : 0x50
memcfg DDR3 ref clock 133 MHz
memcfg DDR3 clock 1596 MHz
memcfg channel assignment: A: 0, B  1, C  2
memcfg channel[0] config (00620020):
   ECC inactive
   enhanced interleave mode on
   rank interleave on
   DIMMA 8192 MB width x8 dual rank, selected
   DIMMB 0 MB width x8 single rank
memcfg channel[1] config (00000000):
   ECC inactive
   enhanced interleave mode off
   rank interleave off
   DIMMA 0 MB width x8 single rank, selected
   DIMMB 0 MB width x8 single rank
CBMEM:
IMD: root @ 0xbffff000 254 entries.
IMD: root @ 0xbfffec00 62 entries.
External stage cache:
IMD: root @ 0xc03ff000 254 entries.
IMD: root @ 0xc03fec00 62 entries.
CBMEM entry for DIMM info: 0xbfffe960
SMM Memory Map
SMRAM       : 0xc0000000 0x800000
 Subregion 0: 0xc0000000 0x300000
 Subregion 1: 0xc0300000 0x100000
 Subregion 2: 0xc0400000 0x400000
MTRR Range: Start=bf800000 End=c0000000 (Size 800000)
MTRR Range: Start=c0000000 End=c0800000 (Size 800000)
MTRR Range: Start=ff000000 End=0 (Size 1000000)
FMAP: area COREBOOT found @ 810200 (4128256 bytes)
CBFS @ 810200 size 3efe00
CBFS: 'COREBOOT Locator' located CBFS at [810200:c00000)
CBFS: Locating 'fallback/postcar'
CBFS: Found @ offset 4c600 size 4ac8
Decompressing stage fallback/postcar @ 0xbffd2fc0 (35536 bytes)
Loading module at 0xbffd3000 with entry 0xbffd3000. filesize: 0x4790 memsize: 0x8a90
Processing 183 relocs. Offset value of 0xbdfd3000
BS: romstage times (exec / console): total (unknown) / 1 ms

coreboot-4.11-692-g6af55e583d-dirty Fri Jan  3 04:30:30 UTC 2020 postcar starting (log level: 7)...
FMAP: area COREBOOT found @ 810200 (4128256 bytes)
CBFS: 'COREBOOT Locator' located CBFS at [810200:c00000)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 1a100 size 1d57f
Decompressing stage fallback/ramstage @ 0xbff69fc0 (425496 bytes)
Loading module at 0xbff6a000 with entry 0xbff6a000. filesize: 0x3dff8 memsize: 0x67dd8
Processing 6147 relocs. Offset value of 0xbf16a000
BS: postcar times (exec / console): total (unknown) / 0 ms

coreboot-4.11-692-g6af55e583d-dirty Fri Jan  3 04:30:30 UTC 2020 ramstage starting (log level: 7)...
Normal boot.
Enumerating buses...
Root Device scanning...
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0154] enabled
PCI: 00:01.0 [8086/0151] disabled
PCI: 00:02.0 [8086/0166] enabled
PCI: 00:04.0 [8086/0153] enabled
PCI: 00:14.0 [8086/1e31] enabled
PCI: 00:16.0 [8086/1e3a] enabled
PCI: 00:16.1: Disabling device
PCI: 00:16.1 [8086/1e3b] disabled No operations
PCI: 00:16.2: Disabling device
PCI: 00:16.2 [8086/1e3c] disabled No operations
PCI: 00:16.3: Disabling device
PCI: 00:16.3 [8086/1e3d] disabled No operations
PCI: 00:19.0 [8086/1502] enabled
PCI: 00:1a.0 [8086/1e2d] enabled
PCI: 00:1b.0 [8086/1e20] enabled
PCH: PCIe Root Port coalescing is enabled
PCI: 00:1c.0 [8086/1e10] enabled
PCI: 00:1c.1 [8086/1e12] enabled
PCI: 00:1c.2 [8086/1e14] enabled
PCI: 00:1c.3: Disabling device
PCI: 00:1c.3 [8086/1e16] disabled
PCI: 00:1c.4: Disabling device
PCI: 00:1c.4: check set enabled
PCI: 00:1c.5: Disabling device
PCI: 00:1c.6: Disabling device
PCI: 00:1c.7: Disabling device
PCI: 00:1d.0 [8086/1e26] enabled
PCI: 00:1e.0: Disabling device
PCI: 00:1e.0 [8086/2448] disabled
PCI: 00:1f.0 [8086/1e55] enabled
PCI: 00:1f.2 [8086/1e01] enabled
PCI: 00:1f.3 [8086/1e22] enabled
PCI: 00:1f.5: Disabling device
PCI: 00:1f.5 [8086/1e09] disabled No operations
PCI: 00:1f.6 [8086/1e24] enabled
PCI: Leftover static devices:
PCI: 00:1c.4
PCI: 00:1c.5
PCI: 00:1c.6
PCI: 00:1c.7
PCI: Check your devicetree.cb.
PCI: 00:1c.0 scanning...
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [1180/e823] enabled
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
PCIe: Max_Payload_Size adjusted to 128
Failed to enable LTR for dev = PCI: 01:00.0
scan_bus: bus PCI: 00:1c.0 finished in 0 msecs
PCI: 00:1c.1 scanning...
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [168c/003c] enabled
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
PCIe: Max_Payload_Size adjusted to 128
Failed to enable LTR for dev = PCI: 02:00.0
scan_bus: bus PCI: 00:1c.1 finished in 0 msecs
PCI: 00:1c.2 scanning...
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [1912/0015] enabled
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
PCIe: Max_Payload_Size adjusted to 128
scan_bus: bus PCI: 00:1c.2 finished in 0 msecs
PCI: 00:1f.0 scanning...
PMH7: ID 05 Revision 12
PNP: 00ff.1 enabled
PNP: 0c31.0 enabled
EC Firmware ID GCHT26WW-3.22, Version 5.01B
H8: BDC detection not implemented. Assuming BDC installed
H8: WWAN installed
PNP: 00ff.2 enabled
scan_bus: bus PCI: 00:1f.0 finished in 4 msecs
PCI: 00:1f.3 scanning...
bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled
bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
scan_bus: bus DOMAIN: 0000 finished in 5 msecs
scan_bus: bus Root Device finished in 5 msecs
done
BS: BS_DEV_ENUMERATE run times (exec / console): 6 / 0 ms
FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes)
MRC: No data in cbmem for 'RW_MRC_CACHE'.
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
PNP: 00ff.1 missing read_resources
PNP: 00ff.2 missing read_resources
Done reading resources.
skipping PNP: 00ff.2@60 fixed resource, size=0!
skipping PNP: 00ff.2@62 fixed resource, size=0!
skipping PNP: 00ff.2@64 fixed resource, size=0!
skipping PNP: 00ff.2@66 fixed resource, size=0!
Setting resources...
TOUUD 0x23b600000 TOLUD 0xc2a00000 TOM 0x200000000
MEBASE 0x1fe000000
IGD decoded, subtracting 32M UMA and 2M GTT
TSEG base 0xc0000000 size 8M
Available memory below 4GB: 3072M
Available memory above 4GB: 5046M
PCI: 00:02.0 10 <- [0x00e1400000 - 0x00e17fffff] size 0x00400000 gran 0x16 mem64
PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io
PCI: 00:04.0 10 <- [0x00e1c30000 - 0x00e1c37fff] size 0x00008000 gran 0x0f mem64
PCI: 00:14.0 10 <- [0x00e1c20000 - 0x00e1c2ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:16.0 10 <- [0x00e1c42000 - 0x00e1c4200f] size 0x00000010 gran 0x04 mem64
PCI: 00:19.0 10 <- [0x00e1c00000 - 0x00e1c1ffff] size 0x00020000 gran 0x11 mem
PCI: 00:19.0 14 <- [0x00e1c3c000 - 0x00e1c3cfff] size 0x00001000 gran 0x0c mem
PCI: 00:19.0 18 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io
PCI: 00:1a.0 10 <- [0x00e1c3f000 - 0x00e1c3f3ff] size 0x00000400 gran 0x0a mem
PCI: 00:1b.0 10 <- [0x00e1c38000 - 0x00e1c3bfff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:1c.0 20 <- [0x00e1b00000 - 0x00e1bfffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 01:00.0 10 <- [0x00e1b00000 - 0x00e1b000ff] size 0x00000100 gran 0x08 mem
PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:1c.1 20 <- [0x00e1800000 - 0x00e1afffff] size 0x00300000 gran 0x14 bus 02 mem
PCI: 02:00.0 10 <- [0x00e1800000 - 0x00e19fffff] size 0x00200000 gran 0x15 mem64
PCI: 02:00.0 30 <- [0x00e1a00000 - 0x00e1a0ffff] size 0x00010000 gran 0x10 romem
PCI: 00:1c.2 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 00:1c.2 24 <- [0x00e0c00000 - 0x00e13fffff] size 0x00800000 gran 0x14 bus 03 prefmem
PCI: 00:1c.2 20 <- [0x00e0000000 - 0x00e08fffff] size 0x00900000 gran 0x14 bus 03 mem
PCI: 03:00.0 10 <- [0x00e0800000 - 0x00e0801fff] size 0x00002000 gran 0x0d mem64
NONE missing set_resources
PCI: 00:1d.0 10 <- [0x00e1c40000 - 0x00e1c403ff] size 0x00000400 gran 0x0a mem
PNP: 00ff.1 missing set_resources
PNP: 00ff.2 missing set_resources
PCI: 00:1f.2 10 <- [0x0000003080 - 0x0000003087] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x0000003090 - 0x0000003093] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x0000003088 - 0x000000308f] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x0000003094 - 0x0000003097] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x00e1c3e000 - 0x00e1c3e7ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00e1c41000 - 0x00e1c410ff] size 0x00000100 gran 0x08 mem64
PCI: 00:1f.6 10 <- [0x00e1c3d000 - 0x00e1c3dfff] size 0x00001000 gran 0x0c mem64
Done setting resources.
Done allocating resources.
BS: BS_DEV_RESOURCES run times (exec / console): 1 / 0 ms
Enabling resources...
PCI: 00:00.0 subsystem <- 17aa/21fa
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 17aa/21fa
PCI: 00:02.0 cmd <- 03
PCI: 00:04.0 cmd <- 02
PCI: 00:14.0 subsystem <- 17aa/21fa
PCI: 00:14.0 cmd <- 102
PCI: 00:16.0 subsystem <- 17aa/21fa
PCI: 00:16.0 cmd <- 02
PCI: 00:19.0 subsystem <- 17aa/21f3
PCI: 00:19.0 cmd <- 103
PCI: 00:1a.0 subsystem <- 17aa/21fa
PCI: 00:1a.0 cmd <- 102
PCI: 00:1b.0 subsystem <- 17aa/21fa
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0013
PCI: 00:1c.0 subsystem <- 17aa/21fa
PCI: 00:1c.0 cmd <- 106
PCI: 00:1c.1 bridge ctrl <- 0013
PCI: 00:1c.1 subsystem <- 17aa/21fa
PCI: 00:1c.1 cmd <- 106
PCI: 00:1c.2 bridge ctrl <- 0013
PCI: 00:1c.2 subsystem <- 17aa/21fa
PCI: 00:1c.2 cmd <- 107
PCI: 00:1d.0 subsystem <- 17aa/21fa
PCI: 00:1d.0 cmd <- 102
PCI: 00:1f.0 subsystem <- 17aa/21fa
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.2 subsystem <- 17aa/21fa
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 17aa/21fa
PCI: 00:1f.3 cmd <- 103
PCI: 00:1f.6 subsystem <- 17aa/21fa
PCI: 00:1f.6 cmd <- 02
PCI: 01:00.0 subsystem <- 17aa/21fa
PCI: 01:00.0 cmd <- 06
PCI: 02:00.0 cmd <- 02
PCI: 03:00.0 cmd <- 02
done.
Found TPM ST33ZP24 by ST Microelectronics
TPM: Startup
TPM: command 0x99 returned 0x0
TPM: Asserting physical presence
TPM: command 0x4000000a returned 0x0
TPM: command 0x65 returned 0x0
TPM: flags disable=0, deactivated=0, nvlocked=1
TPM: setup succeeded
BS: BS_DEV_INIT entry times (exec / console): 61 / 0 ms
Initializing devices...
Root Device init
Root Device init finished in 0 msecs
CPU_CLUSTER: 0 init
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
0x0000000100000000 - 0x000000023b600000 size 0x13b600000 type 6
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
CPU physical address size: 36 bits
MTRR: default type WB/UC MTRR counts: 3/5.
MTRR: WB selected as default type.
MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

CPU has 2 cores, 4 threads enabled.
Setting up SMI for CPU
Will perform SMM setup.
FMAP: area COREBOOT found @ 810200 (4128256 bytes)
CBFS: 'COREBOOT Locator' located CBFS at [810200:c00000)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 13880 size 6800
microcode: sig=0x306a9 pf=0x10 revision=0x21
CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
Processing 16 relocs. Offset value of 0x00030000
Attempting to start 3 APs
Waiting for 10ms after sending INIT.
Waiting for 1st SIPI to complete...done.
Waiting for 2nd SIPI to complete...AP: slot 1 apic_id 1.
done.
AP: slot 2 apic_id 3.
AP: slot 3 apic_id 2.
Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a8 memsize: 0x1a8
Processing 13 relocs. Offset value of 0x00038000
SMM Module: stub loaded at 0x00038000. Will call 0xbff8ed5b(0x00000000)
Installing SMM handler to 0xc0000000
Loading module at 0xc0010000 with entry 0xc0010626. filesize: 0x1d10 memsize: 0x5d68
Processing 84 relocs. Offset value of 0xc0010000
Loading module at 0xc0008000 with entry 0xc0008000. filesize: 0x1a8 memsize: 0x1a8
Processing 13 relocs. Offset value of 0xc0008000
SMM Module: placing jmp sequence at 0xc0007c00 rel16 0x03fd
SMM Module: placing jmp sequence at 0xc0007800 rel16 0x07fd
SMM Module: placing jmp sequence at 0xc0007400 rel16 0x0bfd
SMM Module: stub loaded at 0xc0008000. Will call 0xc0010626(0x00000000)
Initializing Southbridge SMI...

New SMBASE 0xc0000000
In relocation handler: cpu 0
New SMBASE=0xc0000000 IEDBASE=0xc0400000
Writing SMRR. base = 0xc0000006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
New SMBASE 0xbffffc00
In relocation handler: cpu 1
New SMBASE=0xbffffc00 IEDBASE=0xc0400000
Writing SMRR. base = 0xc0000006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
New SMBASE 0xbffff400
In relocation handler: cpu 3
New SMBASE=0xbffff400 IEDBASE=0xc0400000
Writing SMRR. base = 0xc0000006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
New SMBASE 0xbffff800
In relocation handler: cpu 2
New SMBASE=0xbffff800 IEDBASE=0xc0400000
Writing SMRR. base = 0xc0000006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
Initializing CPU #0
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
CPU: platform id 4
CPU: cpuid(1) 0x306a9
CPU: AES supported
CPU: TXT supported
CPU: VT supported
Setting up local APIC...
 apic_id: 0x00 done.
VMX status: enabled
IA32_FEATURE_CONTROL status: locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 2600
Turbo is available but hidden
Turbo is available and visible
CPU #0 initialized
Initializing CPU #1
Initializing CPU #2
Initializing CPU #3
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
Enabling cache
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
CPU: platform id 4
CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
CPU: cpuid(1) 0x306a9
CPU: platform id 4
CPU: AES supported
CPU: TXT supported
CPU: VT supported
CPU: cpuid(1) 0x306a9
Setting up local APIC...
CPU: AES supported
CPU: TXT supported
CPU: VT supported
CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
Setting up local APIC...
 apic_id: 0x03 done.
CPU: platform id 4
VMX status: enabled
 apic_id: 0x02 done.
IA32_FEATURE_CONTROL status: locked
VMX status: enabled
CPU: cpuid(1) 0x306a9
IA32_FEATURE_CONTROL status: locked
CPU: AES supported
CPU: TXT supported
CPU: VT supported
Setting up local APIC...
 apic_id: 0x01 done.
VMX status: enabled
model_x06ax: energy policy set to 6
IA32_FEATURE_CONTROL status: locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 2600
CPU #2 initialized
model_x06ax: frequency set to 2600
CPU #3 initialized
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 2600
CPU #1 initialized
bsp_do_flight_plan done after 7 msecs.
Initializing southbridge SMI...
SMI_STS: 
GPE0_STS: GPIO15 GPIO14 GPIO11 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO0 
ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0 
TCO_STS: 
Locking SMM.
CPU_CLUSTER: 0 init finished in 21 msecs
PCI: 00:00.0 init
Disabling PEG12.
Disabling PEG11.
Disabling PEG10.
Disabling PEG60.
Disabling Device 7.
Disabling PEG IO clock.
Set BIOS_RESET_CPL
CPU TDP: 35 Watts
PCI: 00:00.0 init finished in 1 msecs
PCI: 00:02.0 init
GT Power Management Init
IVB GT2 25W-35W Power Meter Weights
FMAP: area COREBOOT found @ 810200 (4128256 bytes)
CBFS: 'COREBOOT Locator' located CBFS at [810200:c00000)
CBFS: Locating 'pci8086,0166.rom'
CBFS: Found @ offset 3c580 size 10000
In CBFS, ROM address for PCI: 00:02.0 = 0xffc4c7c8
Copying VGA ROM Image from 0xffc4c7c8 to 0xc0000, 0x10000 bytes
pci_cfg_read(): Config read access invalid device! bus: 00 (00), devfn: f8 (10), offs: 02
Stack unclean, initialization probably NOT COMPLETE!
VGA Option ROM was run
GT Power Management Init (post VBIOS)
PCI: 00:02.0 init finished in 13 msecs
PCI: 00:04.0 init
PCI: 00:04.0 init finished in 0 msecs
PCI: 00:14.0 init
XHCI: Setting up controller.. done.
PCI: 00:14.0 init finished in 0 msecs
PCI: 00:16.0 init
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : NO
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Normal
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : uKernel Phase
ME: Power Management Event  : Clean Moff->Mx wake
ME: Progress Phase State    : Unknown 0x00
ME: BIOS path: Normal
ME: Extend SHA-256: e4296030ae179336fc242e1a495f7121e9bea777ff01a32141277ff3e64e84b8
ME: MBP item header 00020103
ME: MBP item header 00050102
ME: MBP item header 00020501
ME: MBP item header 00020201
ME: MBP item header 00020104
ME: unknown mbp item id 0x104! Skipping
ME: MBP item header 02030101
ME: MBP item header 02060301
ME: MBP item header 02090401
ME: found version 8.1.20.1336
ME Capability: Full Network manageability                :  enabled
ME Capability: Regular Network manageability             : disabled
ME Capability: Manageability                             :  enabled
ME Capability: Small business technology                 : disabled
ME Capability: Level III manageability                   : disabled
ME Capability: IntelR Anti-Theft (AT)                    :  enabled
ME Capability: IntelR Capability Licensing Service (CLS) :  enabled
ME Capability: IntelR Power Sharing Technology (MPC)     :  enabled
ME Capability: ICC Over Clocking                         :  enabled
ME Capability: Protected Audio Video Path (PAVP)         :  enabled
ME Capability: IPV6                                      :  enabled
ME Capability: KVM Remote Control (KVM)                  :  enabled
ME Capability: Outbreak Containment Heuristic (OCH)      : disabled
ME Capability: Virtual LAN (VLAN)                        :  enabled
ME Capability: TLS                                       :  enabled
ME Capability: Wireless LAN (WLAN)                       :  enabled
PCI: 00:16.0 init finished in 140 msecs
PCI: 00:19.0 init
PCI: 00:19.0 init finished in 0 msecs
PCI: 00:1a.0 init
EHCI: Setting up controller.. done.
PCI: 00:1a.0 init finished in 0 msecs
PCI: 00:1b.0 init
Azalia: base = e1c38000
Azalia: codec_mask = 09
Azalia: Initializing codec #3
Azalia: codec viddid: 80862806
Azalia: verb_size: 16
Azalia: verb loaded.
Azalia: Initializing codec #0
Azalia: codec viddid: 10ec0269
Azalia: verb_size: 76
Azalia: verb loaded.
PCI: 00:1b.0 init finished in 5 msecs
PCI: 00:1c.0 init
Initializing PCH PCIe bridge.
PCI: 00:1c.0 init finished in 0 msecs
PCI: 00:1c.1 init
Initializing PCH PCIe bridge.
PCI: 00:1c.1 init finished in 0 msecs
PCI: 00:1c.2 init
Initializing PCH PCIe bridge.
PCI: 00:1c.2 init finished in 0 msecs
PCI: 00:1d.0 init
EHCI: Setting up controller.. done.
PCI: 00:1d.0 init finished in 0 msecs
PCI: 00:1f.0 init
pch: lpc_init
PCH: detected QM77, device id: 0x1e55, rev id 0x4
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
Set power off after power failure.
NMI sources enabled.
PantherPoint PM init
RTC: failed = 0x0
RTC Init
Disabling ACPI via APMC:
done.
pch_spi_init
PCI: 00:1f.0 init finished in 0 msecs
PCI: 00:1f.2 init
SATA: Initializing...
SATA: Controller in AHCI mode.
ABAR: 0xe1c3e000
PCI: 00:1f.2 init finished in 0 msecs
PCI: 00:1f.3 init
PCI: 00:1f.3 init finished in 0 msecs
PCI: 00:1f.6 init
PCI: 00:1f.6 init finished in 0 msecs
PCI: 01:00.0 init
PCI: 01:00.0 init finished in 0 msecs
PCI: 02:00.0 init
PCI: 02:00.0 init finished in 0 msecs
PCI: 03:00.0 init
PCI: 03:00.0 init finished in 0 msecs
PNP: 00ff.2 init
PNP: 00ff.2 init finished in 0 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:54 init
I2C: 01:54 init finished in 0 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:55 init
I2C: 01:55 init finished in 0 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:56 init
I2C: 01:56 init finished in 0 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:57 init
I2C: 01:57 init finished in 0 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5c init
Locking EEPROM RFID
init EEPROM done
I2C: 01:5c init finished in 24 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5d init
I2C: 01:5d init finished in 0 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5e init
I2C: 01:5e init finished in 0 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5f init
I2C: 01:5f init finished in 0 msecs
Devices initialized
BS: BS_DEV_INIT run times (exec / console): 208 / 0 ms
Finalize devices...
PCI: 00:1f.0 final
flash size 0xc00000 bytes
SF: Detected Opaque HW-sequencing with sector size 0x1000, total 0xc00000
Devices finalized
BS: BS_POST_DEVICE run times (exec / console): 48 / 0 ms
FMAP: area COREBOOT found @ 810200 (4128256 bytes)
CBFS: 'COREBOOT Locator' located CBFS at [810200:c00000)
CBFS: Locating 'fallback/dsdt.aml'
CBFS: Found @ offset 51100 size 39b0
FMAP: area COREBOOT found @ 810200 (4128256 bytes)
CBFS: 'COREBOOT Locator' located CBFS at [810200:c00000)
CBFS: Locating 'fallback/slic'
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at bff2d000.
ACPI:    * FACS
ACPI:    * DSDT
ACPI:    * FADT
ACPI: added table 1/32, length now 40
ACPI:     * SSDT
Found 1 CPU(s) with 4 core(s) each.
PSS: 2601MHz power 35000 control 0x2100 status 0x2100
PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00
PSS: 2400MHz power 31561 control 0x1800 status 0x1800
PSS: 2200MHz power 28247 control 0x1600 status 0x1600
PSS: 2000MHz power 25084 control 0x1400 status 0x1400
PSS: 1800MHz power 22064 control 0x1200 status 0x1200
PSS: 1600MHz power 19135 control 0x1000 status 0x1000
PSS: 1400MHz power 16344 control 0xe00 status 0xe00
PSS: 1200MHz power 13666 control 0xc00 status 0xc00
PSS: 2601MHz power 35000 control 0x2100 status 0x2100
PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00
PSS: 2400MHz power 31561 control 0x1800 status 0x1800
PSS: 2200MHz power 28247 control 0x1600 status 0x1600
PSS: 2000MHz power 25084 control 0x1400 status 0x1400
PSS: 1800MHz power 22064 control 0x1200 status 0x1200
PSS: 1600MHz power 19135 control 0x1000 status 0x1000
PSS: 1400MHz power 16344 control 0xe00 status 0xe00
PSS: 1200MHz power 13666 control 0xc00 status 0xc00
PSS: 2601MHz power 35000 control 0x2100 status 0x2100
PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00
PSS: 2400MHz power 31561 control 0x1800 status 0x1800
PSS: 2200MHz power 28247 control 0x1600 status 0x1600
PSS: 2000MHz power 25084 control 0x1400 status 0x1400
PSS: 1800MHz power 22064 control 0x1200 status 0x1200
PSS: 1600MHz power 19135 control 0x1000 status 0x1000
PSS: 1400MHz power 16344 control 0xe00 status 0xe00
PSS: 1200MHz power 13666 control 0xc00 status 0xc00
PSS: 2601MHz power 35000 control 0x2100 status 0x2100
PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00
PSS: 2400MHz power 31561 control 0x1800 status 0x1800
PSS: 2200MHz power 28247 control 0x1600 status 0x1600
PSS: 2000MHz power 25084 control 0x1400 status 0x1400
PSS: 1800MHz power 22064 control 0x1200 status 0x1200
PSS: 1600MHz power 19135 control 0x1000 status 0x1000
PSS: 1400MHz power 16344 control 0xe00 status 0xe00
PSS: 1200MHz power 13666 control 0xc00 status 0xc00
Generating ACPI PIRQ entries
\_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0
ACPI:    * H8
H8: BDC detection not implemented. Assuming BDC installed
H8: WWAN installed
ACPI: added table 2/32, length now 44
ACPI:    * MCFG
ACPI: added table 3/32, length now 48
ACPI:    * TCPA
TCPA log created at 0xbff1c000
ACPI: added table 4/32, length now 52
ACPI:    * MADT
ACPI: added table 5/32, length now 56
current = bff32a30
ACPI:     * DMAR
ACPI: added table 6/32, length now 60
current = bff32b00
FMAP: area COREBOOT found @ 810200 (4128256 bytes)
CBFS: 'COREBOOT Locator' located CBFS at [810200:c00000)
CBFS: Locating 'vbt.bin'
CBFS: Found @ offset 3b800 size 599
Found a VBT of 4281 bytes after decompression
GMA: Found VBT in CBFS
GMA: Found valid VBT in CBFS
ACPI:    * HPET
ACPI: added table 7/32, length now 64
ACPI: done.
ACPI tables: 31552 bytes.
smbios_write_tables: bff1b000
Create SMBIOS type 17
SMBIOS tables: 815 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 2fe9
Writing coreboot table at 0xbff51000
FMAP: area COREBOOT found @ 810200 (4128256 bytes)
CBFS: 'COREBOOT Locator' located CBFS at [810200:c00000)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 3be00 size 70c
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000fffff: RESERVED
 3. 0000000000100000-00000000bff1afff: RAM
 4. 00000000bff1b000-00000000bff69fff: CONFIGURATION TABLES
 5. 00000000bff6a000-00000000bffd1fff: RAMSTAGE
 6. 00000000bffd2000-00000000bfffffff: CONFIGURATION TABLES
 7. 00000000c0000000-00000000c29fffff: RESERVED
 8. 00000000f0000000-00000000f3ffffff: RESERVED
 9. 00000000fed40000-00000000fed44fff: RESERVED
10. 00000000fed90000-00000000fed91fff: RESERVED
11. 0000000100000000-000000023b5fffff: RAM
FMAP: area COREBOOT found @ 810200 (4128256 bytes)
CBFS: 'COREBOOT Locator' located CBFS at [810200:c00000)
Wrote coreboot table at: 0xbff51000, 0xa78 bytes, checksum a9aa
coreboot table: 2704 bytes.
IMD ROOT    0. 0xbffff000 0x00001000
IMD SMALL   1. 0xbfffe000 0x00001000
CONSOLE     2. 0xbffde000 0x00020000
TIME STAMP  3. 0xbffdd000 0x00000910
ROMSTG STCK 4. 0xbffdc000 0x00001000
AFTER CAR   5. 0xbffd2000 0x0000a000
RAMSTAGE    6. 0xbff69000 0x00069000
SMM BACKUP  7. 0xbff59000 0x00010000
COREBOOT    8. 0xbff51000 0x00008000
ACPI        9. 0xbff2d000 0x00024000
ACPI GNVS  10. 0xbff2c000 0x00001000
TCPA TCGLOG11. 0xbff1c000 0x00010000
SMBIOS     12. 0xbff1b000 0x00000800
IMD small region:
  IMD ROOT    0. 0xbfffec00 0x00000400
  FMAP        1. 0xbfffeb20 0x000000e0
  MEM INFO    2. 0xbfffe960 0x000001b9
  ROMSTAGE    3. 0xbfffe940 0x00000004
BS: BS_WRITE_TABLES run times (exec / console): 30 / 0 ms
FMAP: area COREBOOT found @ 810200 (4128256 bytes)
CBFS: 'COREBOOT Locator' located CBFS at [810200:c00000)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 72280 size 10c11
Checking segment from ROM address 0xffc824b8
Payload being loaded at below 1MiB without region being marked as RAM usable.
Checking segment from ROM address 0xffc824d4
Loading segment from ROM address 0xffc824b8
  code (compression=1)
  New segment dstaddr 0x000e0280 memsize 0x1fd80 srcaddr 0xffc824f0 filesize 0x10bd9
Loading Segment: addr: 0x000e0280 memsz: 0x000000000001fd80 filesz: 0x0000000000010bd9
using LZMA
Loading segment from ROM address 0xffc824d4
  Entry Point 0x000fd25e
BS: BS_PAYLOAD_LOAD run times (exec / console): 26 / 0 ms
ICH-NM10-PCH: watchdog disabled
Jumping to boot code at 0x000fd25e(0xbff51000)
SeaBIOS (version rel-1.13.0-0-gf21b5a4)
BUILD: gcc: (coreboot toolchain vd70f5fae1c 2019-05-26) 8.3.0 binutils: (GNU Binutils) 2.32
Found coreboot cbmem console @ bffde000
Found mainboard LENOVO ThinkPad X230
Relocating init from 0x000e1960 to 0xbfecdd60 (size 53760)
Found CBFS header at 0xffc10238
multiboot: eax=bffa6d80, ebx=bffa6ce4
Found 18 PCI devices (max PCI bus is 03)
Copying SMBIOS entry point from 0xbff1b000 to 0x000f6780
Copying ACPI RSDP from 0xbff2d000 to 0x000f6750
Using pmtimer, ioport 0x508
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version rel-1.13.0-0-gf21b5a4)
Machine UUID 60603d81-5212-11cb-a5da-889ab1ffde28
XHCI init on dev 00:14.0: regs @ 0xe1c20000, 8 ports, 32 slots, 32 byte contexts
XHCI    protocol USB  2.00, 4 ports (offset 1), def 3001
XHCI    protocol USB  3.00, 4 ports (offset 5), def 1000
XHCI    extcap 0xc1 @ 0xe1c28040
XHCI    extcap 0xc0 @ 0xe1c28070
XHCI    extcap 0x1 @ 0xe1c28330
XHCI init on dev 03:00.0: regs @ 0xe0800000, 4 ports, 32 slots, 64 byte contexts
XHCI    extcap 0x1 @ 0xe0800500
XHCI    protocol USB  3.00, 2 ports (offset 1), def 0
XHCI    protocol USB  2.00, 2 ports (offset 3), def 0
XHCI    extcap 0xc0 @ 0xe0800540
XHCI    extcap 0xa @ 0xe0800550
EHCI init on dev 00:1a.0 (regs=0xe1c3f020)
EHCI init on dev 00:1d.0 (regs=0xe1c40020)
AHCI controller at 00:1f.2, iobase 0xe1c3e000, irq 10
Searching bootorder for: /pci@i0cf8/pci-bridge@1c/*@0
Found 0 lpt ports
Found 0 serial ports
Searching bootorder for: /rom@img/memtest
Searching bootorder for: /rom@img/nvramcui
Searching bootorder for: /rom@img/coreinfo
Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
AHCI/0: Set transfer mode to UDMA-6
Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0
AHCI/0: registering: "AHCI/0: CT250BX100SSD1 ATA-9 Hard-Disk (232 GiBytes)"
XHCI no devices found
XHCI no devices found
Initialized USB HUB (0 ports used)
WARNING - Timeout at ps2_recvbyte:182!
Discarding ps2 data aa (status=11)
Discarding ps2 data e0 (status=11)
Discarding ps2 data 0f (status=11)
Discarding ps2 data e0 (status=11)
Discarding ps2 data f0 (status=11)
Discarding ps2 data 0f (status=11)
WARNING - Timeout at ps2_recvbyte:182!
PS2 keyboard initialized
WARNING - Timeout at ehci_wait_td:517!
ehci pipe=0xbfec6880 cur=bfec1dc0 tok=80080d80 next=bfec1e00 td=0xbfec1dc0 status=80080d80
Initialized USB HUB (0 ports used)
All threads complete.
Scan for option roms

Press ESC for boot menu.

Turning on vga text mode console
SeaBIOS (version rel-1.13.0-0-gf21b5a4)
Machine UUID 60603d81-5212-11cb-a5da-889ab1ffde28
Searching bootorder for: HALT
drive 0x000f66e0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=488397168
Space available for UMB: d0000-ed800, f5fa0-f66e0
Returned 163840 bytes of ZoneHigh
e820 map has 9 items:
  0: 0000000000000000 - 000000000009fc00 = 1 RAM
  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
  3: 0000000000100000 - 00000000bff03000 = 1 RAM
  4: 00000000bff03000 - 00000000c2a00000 = 2 RESERVED
  5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
  6: 00000000fed40000 - 00000000fed45000 = 2 RESERVED
  7: 00000000fed90000 - 00000000fed92000 = 2 RESERVED
  8: 0000000100000000 - 000000023b600000 = 1 RAM
enter handle_19:
  NULL
Booting from Hard Disk...
Booting from 0000:7c00

Th3Fanbus commented 4 years ago

The interesting part got cut off, because it doesn't fit in pre-RAM console buffer. Basically what happened is that raminit failed and one channel got disabled. You can get complete logs by using flashconsole:

Enable flashconsole in Kconfig
Flash coreboot.rom to the flash chips
Power off
Power on
Read back the flashchips into coreboot_with_log.rom
Use cbfstool to extract the log from coreboot_with_log.rom

gjikia commented 4 years ago

@jm2 Did you manage to solve this problem? I am having the same issue: only one module from 2x8GB of G.Skill, DDR3L-1600 SO-DIMM PC3L-12800S is recognized by coreboot/skulls. Recompiling coreboot with the option IGNORE_XMP_MAX_DIMMS mentioned on reddit did not help unfortunately.

jm2 commented 4 years ago

Unfortunately not yet. I don't use the ThinkPads frequently so the priority of building a custom coreboot image to debug this is pretty low for me. If someone has a prebuilt and tested logging-enabled coreboot image for the x230 or x230t and can be safely flashed onto an ivyra1n-unlocked thinkpad, I'm happy to test and report back.

freed00m commented 4 years ago

One day, my DDR3 stick also stoped working and I've discovered it was just oxidization on the pins. Few round with alcohol around the pins on the ram fixed it and 2nd RAM stick started to load again.

jm2 commented 3 years ago

I can confirm that a second flash on both machines (upgrading to the latest release) was able to resolve the issue on both systems where re-seating the RAM didn't work. It's hard to say if a newer release fixed the issue, or if the upgrade sorted out some flash anomaly from the initial conversion to skulls. It looks like this solution works for quite a few cases like this according to https://github.com/merge/skulls/issues/116 and others.

merge / skulls

Only one RAM stick recognized with DDR3L #144