NickQian
commented
6 years ago it's 256bit aligned. I observed a case that if last 5 bit of the address is 'b00100(not 'b00000), then it will be loaded to CONBLK_AD as 'b00000. The 1 will be removed then get a wrong bus address. I don't why has not caused trouble( when the sample quantity is 40,80,....200,...2000, it has no problem. But I believe that they already tested more different "channels[channel].subcycle_time_us / pulse_width_incr_us" cases). I simply add a offset to get address 256bit aligned in the get_cb() function but this can caused other problem. your idea that swap the data layout should be a good method.
Hi, I've been reviewing v2 branch of this code, and have had it working on my Pi 2. However, I also came across the statement "The [control block[ address must be 256 bit aligned and so the bottom 5 bits cannot be set and will read back as zero." BCM2835 ARM Peripherals p.54 section "0_NEXTCONBK ...". The way the data is laid out in memory, the memory allocated will be paged aligned (good), the sample data (of variable length * 4 byte) is positioned first, then the control blocks are laid out (see function get_cb). By my calculation, the control blocks will be 128 bit aligned, but may not be 256 bit aligned if there is an odd number of samples. It may be that the data sheet is wrong, or that the sample data length will always be even, or some other reason why this is not a bug, (or I could be wrong :-). In any case, it would be fairly trivial to fix the fault by swapping the data layout, so that the control blocks appear at the start of the memory (on the page boundary), followed by the sample data. Cheers, Steve