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mgharish005 / vlsi_design

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Issue with a always block latching garbage value #2

Closed akrish21 closed 8 years ago

akrish21 commented 8 years ago

Yovs,

In rtl/divider/divider.v I have a simple always block which goes as

always @(posedge clk) begin if(reset) begin g_dividend_Q <= 16'd0; g_divider_Q <= 16'd0; end else begin g_dividend_Q <= g_dividend_In; g_divider_Q <= g_divider_In; end end

the cycle my g_dividend_In is changing, g_dividend_Q changes to a garbage value. then one cycle later it changes to correct value. Why/How can this happen ?

I have attached a pic of waveform for reference. error1

Any suggestions to avoid this ? @mgharish005 @kgopala1989

kgopala1989 commented 8 years ago

Does this happen everytime the input changes? On Apr 2, 2016 1:33 PM, "akrish21" notifications@github.com wrote:

Yovs,

In rtl/divider/divider.v I have a simple always block which goes as

always @(posedge clk) begin if(reset) begin g_dividend_Q <= 16'd0; g_divider_Q <= 16'd0; end else begin g_dividend_Q <= g_dividend_In; g_divider_Q <= g_divider_In; end end

the cycle my g_dividend_In is changing, g_dividend_Q changes to a garbage value. then one cycle later it changes to correct value. Why/How can this happen ?

I have attached a pic of waveform for reference. [image: error1] https://cloud.githubusercontent.com/assets/15874048/14228846/3eaeb2bc-f8f0-11e5-8d41-12f24a0fa1a5.png

Any suggestions to avoid this ? @mgharish005 https://github.com/mgharish005 @kgopala1989 https://github.com/kgopala1989

— You are receiving this because you were mentioned. Reply to this email directly or view it on GitHub https://github.com/mgharish005/vlsi_design/issues/2

akrish21 commented 8 years ago

yeah ji !. Everytime g_dividend_In changes I see this glitch. The g_dividend_In is actually output of a combi logic. could this mean some timing violation ?

mgharish005 commented 8 years ago

You said g_divident_In is combinational output why is it changing at clock edge ? What other signals does it depend on (any synchronous signals ? ) ?

akrish21 commented 8 years ago

answer found : since I drive combi signals from testbench in active clock edge, which may cause timing violation. Will be driving combi singnals (if needed) in inactive edge of clock hereafter.