Closed GoogleCodeExporter closed 9 years ago
With high-level Turbo Boost support in place (from gj_barr), adding Thuban
support
should be fairly easy.
Unfortunately, I don't have access to respective hardware to test.
Any chance you could test SVN snapshot once the code is committed?
Original comment by kszy...@gmail.com
on 10 Dec 2012 at 6:32
Sure, I can test ti.
Original comment by J.Fi...@gmail.com
on 10 Dec 2012 at 7:07
All right.
Can you check out SVN revision 97 (HEAD) and see how it behaves on Thuban?
Thank you!
Original comment by kszy...@gmail.com
on 11 Dec 2012 at 5:51
Ugh. Pardon me, try revision 98 please (identified critical typo in r97).
Original comment by kszy...@gmail.com
on 11 Dec 2012 at 6:07
Verified (with assistance from good friends).
Used r107.
Original comment by kszy...@gmail.com
on 14 Dec 2012 at 7:48
now it seems to work, thanks
TurionPowerControl trunk-r107 (Turion Power States Optimization and Control -
by blackshard)
Main processor is Family 10h Processor
Family: 0xf Model: 0xa Stepping: 0x0
Extended Family: 0x10 Extended Model: 0xa
Package Type: 0x1 BrandId: 0x40
Machine has 1 nodes
Processor has 6 cores
Processor has 5 p-states
Processor has 1 boost states
Power States table:
-- Node: 0 Core 0
core 0 pstate 0 (pb0) - En:1 VID:10 FID:16 DID:0.00 Freq:3200 VCore:1.4250
core 0 pstate 1 (p0) - En:1 VID:20 FID:11 DID:0.00 Freq:2700 VCore:1.3000
core 0 pstate 2 (p1) - En:1 VID:22 FID:4 DID:0.00 Freq:2000 VCore:1.2750
core 0 pstate 3 (p2) - En:1 VID:26 FID:12 DID:1.00 Freq:1400 VCore:1.2250
core 0 pstate 4 (p3) - En:1 VID:30 FID:0 DID:1.00 Freq:800 VCore:1.1750
-- Node: 0 Core 1
core 1 pstate 0 (pb0) - En:1 VID:10 FID:16 DID:0.00 Freq:3200 VCore:1.4250
core 1 pstate 1 (p0) - En:1 VID:20 FID:11 DID:0.00 Freq:2700 VCore:1.3000
core 1 pstate 2 (p1) - En:1 VID:22 FID:4 DID:0.00 Freq:2000 VCore:1.2750
core 1 pstate 3 (p2) - En:1 VID:26 FID:12 DID:1.00 Freq:1400 VCore:1.2250
core 1 pstate 4 (p3) - En:1 VID:30 FID:0 DID:1.00 Freq:800 VCore:1.1750
-- Node: 0 Core 2
core 2 pstate 0 (pb0) - En:1 VID:10 FID:16 DID:0.00 Freq:3200 VCore:1.4250
core 2 pstate 1 (p0) - En:1 VID:20 FID:11 DID:0.00 Freq:2700 VCore:1.3000
core 2 pstate 2 (p1) - En:1 VID:22 FID:4 DID:0.00 Freq:2000 VCore:1.2750
core 2 pstate 3 (p2) - En:1 VID:26 FID:12 DID:1.00 Freq:1400 VCore:1.2250
core 2 pstate 4 (p3) - En:1 VID:30 FID:0 DID:1.00 Freq:800 VCore:1.1750
-- Node: 0 Core 3
core 3 pstate 0 (pb0) - En:1 VID:10 FID:16 DID:0.00 Freq:3200 VCore:1.4250
core 3 pstate 1 (p0) - En:1 VID:20 FID:11 DID:0.00 Freq:2700 VCore:1.3000
core 3 pstate 2 (p1) - En:1 VID:22 FID:4 DID:0.00 Freq:2000 VCore:1.2750
core 3 pstate 3 (p2) - En:1 VID:26 FID:12 DID:1.00 Freq:1400 VCore:1.2250
core 3 pstate 4 (p3) - En:1 VID:30 FID:0 DID:1.00 Freq:800 VCore:1.1750
-- Node: 0 Core 4
core 4 pstate 0 (pb0) - En:1 VID:10 FID:16 DID:0.00 Freq:3200 VCore:1.4250
core 4 pstate 1 (p0) - En:1 VID:20 FID:11 DID:0.00 Freq:2700 VCore:1.3000
core 4 pstate 2 (p1) - En:1 VID:22 FID:4 DID:0.00 Freq:2000 VCore:1.2750
core 4 pstate 3 (p2) - En:1 VID:26 FID:12 DID:1.00 Freq:1400 VCore:1.2250
core 4 pstate 4 (p3) - En:1 VID:30 FID:0 DID:1.00 Freq:800 VCore:1.1750
-- Node: 0 Core 5
core 5 pstate 0 (pb0) - En:1 VID:10 FID:16 DID:0.00 Freq:3200 VCore:1.4250
core 5 pstate 1 (p0) - En:1 VID:20 FID:11 DID:0.00 Freq:2700 VCore:1.3000
core 5 pstate 2 (p1) - En:1 VID:22 FID:4 DID:0.00 Freq:2000 VCore:1.2750
core 5 pstate 3 (p2) - En:1 VID:26 FID:12 DID:1.00 Freq:1400 VCore:1.2250
core 5 pstate 4 (p3) - En:1 VID:30 FID:0 DID:1.00 Freq:800 VCore:1.1750
--- Node 0:
Processor Maximum PState: 4
Processor Startup PState: 1
Processor Maximum Operating Frequency: 3200 MHz
Minimum allowed VID: 123 (0.0125V) - Maximum allowed VID 10 (1.4250V)
Processor AltVID: 30 (1.1750V)
Done.
Original comment by J.Fi...@gmail.com
on 14 Dec 2012 at 10:12
Cool.
FYI -- few more turbo/CPB related issues have been identified and fixed.
r112 works fine on all test configurations.
Original comment by kszy...@gmail.com
on 15 Dec 2012 at 7:34
Original issue reported on code.google.com by
J.Fi...@gmail.com
on 28 Sep 2012 at 11:53