Add missing (ZP),Z addressing mode support for 45xx CPUs

[gardners]

As promised, completely re-implemented the missing (ZP),Z addressing modes for 45xx CPUs, to replace old pull request #29

[michaelcmartin]

This looks like it's adding two addressing modes that are not valid for any particular instructions according to the opcode tables. This needs a little reworking to really do the job, but what reworking is necessary depends on what the intended behavior actually is, and I'm not familiar with the 4502 so this isn't immediately obvious to me. Obvious gaps so far are:

• No extensions to the front-end to generate MemoryZ instructions for later collapse to AbsoluteZ or ZeroPageZ
• Opcodes.py does not extend the arrays for the new addressing modes, which means that attempts to actually index them will give IndexErrors
• Opcodes.py shouldn't be edited directly anyway, since it is built by a script from tables and files in the tools subdir
• Testcases for the new instructions should be added to the instruction-assembly tests, possibly with reasonable-looking-but-erroneous instructions as intentional fail cases

I'm willing to provide some guidance and support on some of this but my unfamiliarity with the chip variant means I'll mostly only be of any use with the "integrating with the rest of the internals" part.

[michaelcmartin]

After cross-checking with the Steil's documentation, the VICE techdocs, and ca65's behavior, I'm fairly confident that these capabilities are already present in Ophis 2.1, and the syntax described above is present in the unit tests as well. This cross-check found some ISA anomalies along the way but they've now been fixed in the code generator itself as part of the fix for issue #38.