search

michaeljclark / rv8

RISC-V simulator for x86-64
https://michaeljclark.github.io/
MIT License
671 stars 97 forks source link

Instruction sequence for bit sign extention #29

Closed jbrandmeyer closed 7 years ago

jbrandmeyer commented 7 years ago

I think that you can perform bit sign extension in fewer instructions than claimed. I'm using an ARMish syntax here (since that's what I'm familiar with...)

; a0: argument ; a1: value less than XLEN for the bit position to be extended addi a1 a1 #-32 ; Assuming 32-bit arch. For RV64 or 128, replace as appropriate neg a1 a1 sll a0 a0 a1 sra a0 a0 a1

Similarly, for signed bit extend by an immediate, you can just perform the left shift and arithmetic right shift.

michaeljclark commented 7 years ago

Thanks. I was looking at codegen for the hacker's delight C fragment. Now you point is out it seems to require less instructions. x86 has BZHI which zeros high bits starting at bit n. neg could could be used for sign extension. I'll update the page...