Implement lazy sign extension for 32-bit operations on RV64

michaeljclark / rv8

RISC-V simulator for x86-64

https://michaeljclark.github.io/

MIT License

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Implement lazy sign extension for 32-bit operations on RV64 #40

Closed michaeljclark closed 7 years ago

michaeljclark commented 7 years ago

The following 32-bit operations are required to sign extend their results:

addw, subw, mulw, divw, remw, divuw, remuw, sllw, srlw, sraw, addiw, slliw, srliw, sraiw

The code currently emits sign extension code after each operation. If the emitter keeps track of the width of the last operation, it would be possible to sign extend the register lazily either when it is used as input to a 64-bit operation or at a branch tail or the end of a trace.

michaeljclark commented 7 years ago

Experiments show that non-local sign extension does not improve performance, and may degrade performance, potentially because the microarchitecture may perform move elimination for adjacent sign extension instructions (possibly handled in the renamer).