michaeljclark / rv8

RISC-V simulator for x86-64
https://michaeljclark.github.io/
MIT License
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Implement address translation in emu/riscv-mmu.h #5

Closed michaeljclark closed 7 years ago

michaeljclark commented 7 years ago

Implement instruction fetch, loads and stores using current privilege level and flags e.g. MSTATUS.{MPRV,PUM,MXR,VM}

Implement a minimal subset of PMA with PMP attributes (emu/riscv-pma.h) to protect M-mode PA from S-mode.

switch (proc.mstatus.vm) {
    case riscv_vm_mbare: /* TODO */ break;
    case riscv_vm_mbb:   /* TODO */ break;
    case riscv_vm_mbid:  /* TODO */ break;
    case riscv_vm_sv32:  /* TODO */ break;
    case riscv_vm_sv39:  /* TODO */ break;
    case riscv_vm_sv48:  /* TODO */ break;
}
michaeljclark commented 7 years ago

Address translation as per privileged spec 1.9.1 has been implemented