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micro-FPGA / riscv-contest-2018

RISCV SoftCPU Contest 2018
Apache License 2.0
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What is a minimal RV32I core that is compliant? #3

Open atthecodeface opened 5 years ago

atthecodeface commented 5 years ago

RV32I does not require a PLIC, but Zephyr 1.13 does not run a riscv-privilege build without one, without modification to the Zephyr OS Core.

Can one build a non-riscv-privilege core (as far as Zephyr 1.13 is concerned) - would this not require modification to Zephyr OS core?

AnttiLukats commented 5 years ago

YES you need at least minimal interrupt handling that complies to the privileged stuff. So you need at least: writeable mtvec, one timer tick interrupt with pending and enable bits as per PLIC. This rules EXCLUDES all designs based on picorv32 as example, any custom style interrupt processing violates the rule requirements.

Dolu1990 commented 5 years ago

Zephyr 1.13 doesn't not require having a PLIC, see https://github.com/zephyrproject-rtos/zephyr/blob/16661304162cc86b95f03077e1fe199d3f738a8e/soc/riscv32/riscv-privilege/Kconfig#L18

AnttiLukats commented 5 years ago

Yes sure no PLIC, if you use machine timer interrupt, this machine timer and interrupt handling has to be compliant to riscv spec.