I loved you EuroForth talk

[PythonLinks]

I am going to watch it a second time.

Okay, I get it. Optional byte addressing is needed for TCP/IP. Thank you. Most appreciated. I would also have done it wrong!

And your verification of division was just brilliant. I was always a bit skeptical of this huge emphasis on verification. Most needed for ASICs,s but for FPGA's??? Your talk convinced me that FPGA's also need it. I wonder what made you suspect there was a problem with division?

Next issue. I think for existing clients, you have to stay with the old version of VHDL. But I think it hugely scares off the new clients. Maybe it would be good to upgrade the code before you retire. then it would be good for another 30 years!

As for me, my thesis proposal was accepted.

Implementation of a Forth Microcontroller Core in an FPGA

The objective is to design the architecture and develop a synthesizable stack machine implementing the Forth language and optimizing the interrupt delays. Here is the proposal.

The developed Verilog module will include program/data memory and selected peripheral systems (general purpose I/O ports) and will be implemented on an FPGA.

As part of the work, the interrupt latency of a test program will be measured and compared with the published results for other microcontrollers, scaling for the clock frequency.

Why do I mention it? Well your design is quite inspirational when it comes to interrupt processing. I had no idea we could do it that way.

Interrupt processing is so important in real time systems. In fact the wikipedia article on Microcontrollers even has a section on interrupt processing.

https://en.wikipedia.org/wiki/Microcontroller#Interrupt_latency

From your documentation, "At 25Mhz, it takes 7 μseconds to put the task to sleep, and start another one. " A Mhz is a million hertz. A μs is a millionth of a second. So in each μs you execute 25 instructions, meaning 7*25 clock cycles to change processes. That seems awfully long for your architecture. Am I doing the math right? I thought I read that you can do it in 6 clock cycles.

Do you like to sail? I have an EU skipper's license.

[microCore-VHDL]

my thesis proposal was accepted.

Congratulations! I am glad as well.

I wonder what made you suspect there was a problem with division?

I had an uneasy feeling, because previously, I only did random tests - those were all ok. After doing the comprehensive test, I found several "missing" overflows. The result was not correct, but the overflowbit was not set either. These have now all been fixed.

Maybe it would be good to upgrade the code before you retire. then it would be good for another 30 years!

I did convert to VHDL-2008 but then a friend wanted to put uCore on an old FPGA board which could not be programmed using 2008. Therefore I converted back to 93. There is nothing wrong with 93 - only some features missing and therefore, a little "wordier" than 2008. Application specific additions to the code should be done using 2008. And numeric_std, unsigned and signed do exist in 93 already. It was a major change when I threw out the old Synopsis libraries using numeric_std instead.

Here is the proposal.

??? Where is it?

the interrupt latency of a test program will be measured

Please note that interrupts will never be disabled when you use uForth's multitasker. This has to do with the implementation of +!, which takes 2 un-interruptible cycles. Therefore, the raw interrupt latency will be 2 cylces for interrupt synchronisation + 2 cycles due to +!, @ etc. @ 25 Mhz (= 40 ns) it should be between 160 - 200 ns. And you don't have to save/restore registers, because everything is on stacks already and the status register is pushed on the stack automatically and restored by the IRET instruction in parallel to doing an EXIT.

meaning 7*25 clock cycles to change processes. That seems awfully long for your architecture.

Take a look at do-wake in multitask.fs. That is the the code that does a task switch. Do-next has to be executed for each task that is not ready to run. In the IF clause you put the current task to sleep and activate a new one. This does not have to be done if the current task is the same as the "new" one, i.e. only this one task is ready to run in the scheduler loop. Do-wake takes at most about 50 cycles = 2 usec. I have no recollection were "7 usec" came from. You are going to find out :)

Because of the "slow" task switch I implemented the words POLL and POLL-TMAX (task_lib.fs). Those will only initiate a task switch when a programmable condition is met or, in the case of POLL-TMAX, a maximum waiting time has elapsed.

[PythonLinks]

Thank you for the clear analysis, and the pointers to the source code. 4 clock cycles sounds about right. Now I need to figure out just how you did that. Right now I am hard at work trying to complete all of the assignments before the end of the semester, later I will come back, read this comment again and dig into the source code.

It is a great point that I can use older VHDL with newer verilog.
No point re implementing all 50 Forth words. I need to figure out how to do the basics, and then reuse what I can find. Particularly since your work is now so well tested, and so portable. There are also several python libraries that generate and verify digital circuits. Ammarath is giving a talk at the upcoming open silicon conference in Paris. Videos will be available after the conference. They may also have some good components. For example, I do not need variable length math operations.

My proposal was all included above. Just a very high level direction. The advice is to make it a general area of interest, so that one does not get stuck later. Actually the proposal that was approved had even less details. (And was in Polish).