Currently in function uart0Init the clk -value is calculated from SystemCoreClock.
SystemCoreClock is main clock divided by SYSAHBCLKDIV. If i use PLL or higher main clock so that i need to set SYSAHBCLKDIV > 1 , the clk is calculated wrongly resulting in higher baudrate as desired.
clk should be calculated from main clock rate e.g. __MAIN_CLOCK as the main clock is used for USART fractional divider (UM10601 Fig 27)
Currently in function uart0Init the clk -value is calculated from SystemCoreClock.
SystemCoreClock is main clock divided by SYSAHBCLKDIV. If i use PLL or higher main clock so that i need to set SYSAHBCLKDIV > 1 , the clk is calculated wrongly resulting in higher baudrate as desired.
clk should be calculated from main clock rate e.g. __MAIN_CLOCK as the main clock is used for USART fractional divider (UM10601 Fig 27)