search

microbuilder / LPC810_CodeBase

Open source code base for the ARM Cortex M0+ LPC810 family from NXP
85 stars 43 forks source link

CPUClock set to 20MHz and zero flash waitstates #4

Closed cpldcpu closed 11 years ago

cpldcpu commented 11 years ago

This is a small update to my previous changes.

I had previously set the CPU core clock to 30Mhz. Unfortunately the LPC810 requires one wait state on flash accesses (default setting) for clocks above 20Mhz. Therefore using 20Mhz at zero flash waitstates should yield the fastest and most predictable code execution timing.

Added wait state initialization to System_init()

cpldcpu commented 11 years ago

A small clean up

I found out the reason why System_init() had to be called manually was the missing __USE_CMSIS define. I added this to the project and removed the call in main().

cpldcpu commented 11 years ago

This should be my final commit for today. After studying the CMSIS documentation I reverted some of my clock system hacks back to the original state.

1) The normal functionality of SystemCoreClock is provided again.

2) Moving the clock definition from the .c to the .h file seems to be allowable for CMSIS: NXP should consider doing this as a standard. I wonder how to contact them properly...

3) Avoiding run time calculation of timing constants is now avoided by not using the global SystemCoreClock, but by directly using __SYSTEM_CLOCK and __MAIN_CLOCK. The latter is the only way to access the peripheral clock anyways.