Closed Thingybob8055 closed 7 months ago
kliuMsft
commented
11 months ago My apologies - the FPGA build setup in this repo is merely a carryover from the original lowRISC ibex repo and has not been updated to supported CHERIoT yet. We have released a separate FPGA repo for CHERIoT at https://github.com/microsoft/cheriot-safe. Right now it only contains RTL design but we hope in a couple of weeks it would be updated with the build and simulation setup.
Thingybob8055
commented
11 months ago Hi, I managed to get it built and upload to the FPGA. I had to make the following quick changes:
In the file ibex_core.core, I added to the files: section:
rtl/cheri_tbre_wrapper.sv
rtl/cheri_stkz.sv
And in the systemverilog file top_artya7.sv, I commented out the line .alert_major_o as this does not seem to be a port in the ibex_top module. (and therefore was causing an error)
After these quick changes, the Arty A7 example was able to synthesise, implement and generate the bit stream and the LEDs blinked in an alternate pattern just like the README.md said.
Is this fine to get the cheriot-ibex running on an FPGA such as the Arty A7?
kliuMsft
commented
11 months ago This is very interesting indeed. I didn't quite expect it to work this way so it is a bit surprise, although a good one. Basically by doing this, you are tying all unmapped inputs on ibex_top to '0' and thus setting up cheriot-ibex in "backward compatibility mode", where it behaves exactly as the unmodified ibex (which supports RV32IMC). That's why you can build the FPGA and run the examples, even though they are just carryovers from the original ibex. However to take advantage of the CHERIoT extension, you will need to make some modifications to the memory system (that's what cheriot-safe does) and use the CHERIoT compiler (https://github.com/CTSRD-CHERI/llvm-project/tree/cheriot) to build C/C++ code. We are working on putting together more information and examples in cheriot-safe as well.
kliuMsft
commented
11 months ago BTW I also updated the top_artya7.sv per your comments. Thanks for pointing it out!
Thingybob8055
commented
11 months ago Hello, Thanks a lot for your detailed answer! Do you have an approximate timeline when I can test out cheriot-safe on an FPFA (as well as software running baremetal on the core). If its no trouble, can you give brief instructions on how I can go about doing it myself for now?
kliuMsft
commented
11 months ago No problem. I want to say very soon - we already have the full RTL in the repo, some barebone documentation and readme /examples on how to run verilator simulations. Next we will add more scripts/examples on how to build FPGA and build software..
I'd say the logical next step for you is to download and install the cheriot LLVM compiler at the link above, which might take a little effort the first time.
kliuMsft
commented
7 months ago I am closing the issue since it's more about the cheriot-safe FPGA (where there are realted discussions already).
Hello, I am investigating in using ibex for my University research project and I have some problems trying to get the example (targeting Artix A7-100T) to build correctly. I took a look in the examples folder:
examples/fpga/artya7and ran the make command from the project root:make build-arty-100 program-artybut throws errors while building and it fails. I will paste the message log in this post.Tools:
requirements.txtfrom project root.pip3 install -r python-requirements.txtOperating System
Ibex Repository commit
Latest commit at the time of writing: ba458abd6f20a558b15bfb763eb533884bf7759f
Build Message
This is my first time posting an issue on GitHub, so please let me know if there is anything I can do to improve the post, and please do not hesitate to ask for more details!