Arty A7 35T support

[marnovandermaas]

I was following the instructions in issue: https://github.com/microsoft/cheriot-safe/issues/3

Neither the hello world nor the charity sanity check are producing any UART output for me while using the Arty A7 with the 35T. Is this because I do not have the 100T or are we expecting these instructions to work for the 35T as well?

[kliuMsft]

The current design really shouldn't fit in 35T - are you sure vivado didn't give you any problem? The design requires roughly 384kB block RAM, while 35T only has a little over 200kB.

[kliuMsft]

That said, you are welcome to experiment with smaller memory (iram, etc) and the source code (stack location mostly). The memory sizes can be easily changed in the fpga top-level verilog.

[marnovandermaas]

You're right, Vivado complains about resource utilization. I will close these issues for now. For completeness here are the errors from the DRC report:

UTLZ-1#1 Error
Resource utilization  - PBlock:ROOT
LUT as Logic over-utilized in Top Level Design (This design requires more LUT as Logic cells than are available in the target device. This design requires 21420 of such cell types but only 20800 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)ROOT
Related violations: <none>

UTLZ-1#2 Error
Resource utilization  - PBlock:ROOT
RAMB18 and RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 198 of such cell types but only 100 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations: <none>

UTLZ-1#3 Error
Resource utilization  - PBlock:ROOT
RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB36/FIFO cells than are available in the target device. This design requires 82 of such cell types but only 50 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations: <none>

UTLZ-1#4 Error
Resource utilization  - PBlock:ROOT
RAMB36E1 over-utilized in Top Level Design (This design requires more RAMB36E1 cells than are available in the target device. This design requires 82 of such cell types but only 50 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)ROOT
Related violations: <none>

UTLZ-1#5 Error
Resource utilization  - PBlock:ROOT
Slice LUTs over-utilized in Top Level Design (This design requires more Slice LUTs cells than are available in the target device. This design requires 24668 of such cell types but only 20800 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)ROOT
Related violations: <none>