Is there any updated documentation on how to use the rdmsr/wrmsr commands on ARM64 targets? The register parameter appears to be an encoding of the op0, op1, CRn, CRm, and op2 bits though it's not intuitive. I've created this macro that I think does the encoding properly but official confirmation/documentation would be appreciated:
Is there any updated documentation on how to use the rdmsr/wrmsr commands on ARM64 targets? The register parameter appears to be an encoding of the op0, op1, CRn, CRm, and op2 bits though it's not intuitive. I've created this macro that I think does the encoding properly but official confirmation/documentation would be appreciated: