mii-key / obsidian-links

manipulate & manage obisidian links
MIT License
105 stars 5 forks source link

Select all #36

Open UndiFineD opened 1 month ago

UndiFineD commented 1 month ago

add a Select all to make linking documents faster

mii-key commented 1 month ago

Please clarify your use case.

UndiFineD commented 1 month ago

I create a new page, write a document, press to create links, and it finds some 200 links to create. having a select all, would speed up my process many minutes per document.

mii-key commented 1 month ago

Thank you for explaining. However, the process you've described is unclear. Perhaps an example would help.

UndiFineD commented 1 month ago

I write technical documentation, lots of jargon, so here is an example

Yosys is an open-source framework for Verilog RTL synthesis. 
It is widely used in the field of digital design automation (EDA) for transforming high-level Hardware description Language (HDL) into gate-level representations. Here are some key aspects of Yosys:

1. **Open-Source Nature**: Yosys is freely available under the ISC license, which allows User to modify, distribute, and use the Software without significant restrictions.

2. **Verilog Support**: Yosys primarily supports the Verilog Hardware description language, which is commonly used in designing digital circuits. It can parse, analyze, and optimize Verilog code.

press to create links, gives a selection of some 200 possible links to create to existing pages, a select all would be really helpful here

the document becomes

[[Yosys]] is an open-source framework for [[Verilog]] [[RTL]] synthesis. 
It is widely used in the field of digital design automation ([[EDA]]) for transforming high-level Hardware description Language ([[HDL]]) into gate-level representations. Here are some key aspects of Yosys:

1. **[[Open-Source Nature]]**: Yosys is freely available under the [[ISC license]], which allows User to modify, distribute, and use the Software without significant restrictions.

2. **[[Verilog Support]]**: Yosys primarily supports the Verilog Hardware description language, which is commonly used in designing [[digital circuits]]. It can parse, analyze, and optimize Verilog code.
mii-key commented 1 month ago

Thank you for the example. I will review it and see what I can do.