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mikestir / fpga-bbc

Acorn BBC Micro on an Altera DE1 FPGA board
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VIA 6522 Timer implementation #1

Closed Rhialto closed 2 years ago

Rhialto commented 2 years ago

Hi! I am working on improving the VIA 6522 shift register implementation in VICE. I'm searching around for reverse engineering details regarding the exact timing of the timer, when it sets the timer 2 interrupt, when the shift register is shifting, and when the SR interrupt flag is set. Earlier I found https://github.com/MiSTer-devel/Apple-II_MiSTer/issues/17 where a different VHDL VIA is show. It is missing the interrupt handling. On the other hand it has a weirdness of the VIA that yours doesn't implement: after a counter reaches 0000, and before it is reloaded from the latch (T1 the whole latch, or T2 just the low latch), it reads FFFF (or xxFF for T2, where xxxx is 1 less than its previous value) for one cycle. Only after that the timer is set to its latch value. This is how shifting a bit from the shift register takes N+2 cycles if T2 is set to N. See also https://sourceforge.net/p/opencbm/code/ci/master/tree/opencbm/cbmrpm41/cbmrpm41.a65 for research by Wolfgang Moser. Unfortunately he leaves interrupts unmentioned... So, do you know some other, hopefully cycle-perfect, vhdl version of the VIA, or something like visual 6502 for the VIA?

fordp2002 commented 2 years ago

I think there is a better VIA version as part of Beebfpga. It may be worth trying that.

mikestir commented 2 years ago

I'm not aware of anything that stands out for being cycle accurate, but I asked around a bit and came across https://github.com/skibo/Pet2001_Arty/blob/master/src/rtl/pet2001hw/via6522.v (and there's loads of others, many of which also seem to be based on MikeJ's, or are just very simple implementations of the ports only).

There's a die shot on visual 6502 as well: http://www.visual6502.org/images/6522/MOS_6522_die_20x_top2_4631w.png

Rhialto commented 2 years ago

Thanks for the info! I think the via6522.v is verilog, right, not vhdl? I think I'll need to find a Verilog simulator for Linux then. For VHDL I found ghdl, https://ghdl.github.io/ghdl/about.html).

@fordp2002 : I like the comment in https://github.com/hoglet67/BeebFpga/blob/master/src/common/m6522.vhd : "version 005 Many fixes to all areas, VIA now passes all VICE tests" :-)