Hardware vulnerabilities from the "Security Risc" paper

[orlitzky]

The paper A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs lists several hardware attacks against RISC-V cpus. There's also a video from the IEEE Symposium on Security and Privacy presentation.

In particular,

• Cache+Time works using fence.i
• Flush+Fault works using dcache.civa and icache.iva
• Flush+Reload works using dcache.civa
• Flush+Flush works using dcache.civa
• Fence+Flush works using fence.i

Test programs can be found in https://github.com/cispa/Security-RISC

These are well-known exploits so it would be good to start mitigating them. Perhaps a good first step is to make dcache.civa and icache.iva privileged by default (with a kernel flag)?