minerva-cpu minerva issues - Githubissues

minerva-cpu / minerva

A 32-bit RISC-V soft processor

Other

301 stars 32 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

Issue with LiteX running Minerva

#17 TarikHamedovic opened 3 weeks ago
1
pyproject: migrate to pdm-build

#16 whitequark closed 1 year ago
3
Shape: Convert to non-obsolete way of expressing shapes

#15 galibert closed 1 year ago
1
wishbone: Convert to the wishbone_soc interfacing, for better interoperability

#14 galibert opened 1 year ago
1
Fix link to Amaranth installation instructions

#13 twam closed 2 years ago
1
Require python >= 3.6 as documented in Readme

#12 twam closed 2 years ago
1
Fix nmigen include in cli.py

#11 twam closed 2 years ago
1
nMigen has been renamed to Amaranth HDL

#10 whitequark closed 2 years ago
1
Some structural changes:

#9 BracketMaster closed 4 years ago
14
JTAG: can't read PC, can't step, can't attach gdb

#8 strobo5 closed 4 years ago
3
Minerva currently broken with nMigen master

#7 enjoy-digital closed 4 years ago
2
Adding the GitHub default .gitignore file for a Python project.

#6 mithro closed 4 years ago
2
Unable to simulate with Verilator: Circular logic error

#5 enjoy-digital closed 4 years ago
4
Request for using nmigen v0.1rc1

#4 ghost closed 4 years ago
0
Fixes for successful synthesis in ISE 14.7

#3 strobo5 closed 4 years ago
7
Quick start example won't produce output

#2 AntonBabushkin opened 5 years ago
0
No module named 'jtagtap'

#1 AntonBabushkin opened 5 years ago
0