Closed egrath closed 1 year ago
Carts are loaded into SDRAM, so I think it's not impossible.
http://wiki.icomp.de/wiki/Retro_Replay Some reference docs for the brave who want to implement it
It seems that the heavy lifting of implementing it for FPGA64 has already been done by the MISTer people, so it's maybe just a matter of copying over the necessary VHDL code - unfortunately i'm too little into FPGA development :-/
// Retro Replay - (64k 8x8k banks + 32K RAM)
36: begin
IOE_ena <= allow_freeze;
IOF_ena <= allow_freeze & ~reu_map;
IOE_wr_ena <= allow_freeze & romL_we;
IOF_wr_ena <= allow_freeze & romL_we & ~reu_map;
bank_lo <= ~romL_we ? bank_hi : allow_bank ? bank_hi[1:0] : 2'b00;
IOE_bank <= ~romL_we ? bank_hi : allow_bank ? bank_hi[1:0] : 2'b00;
IOF_bank <= ~romL_we ? bank_hi : allow_bank ? bank_hi[1:0] : 2'b00;
if(nmi) allow_freeze <= 0;
if(!init_n || freeze_crt) begin
cart_disable <= 0;
exrom_overide <= 1;
game_overide <= 0;
romL_we <= 0;
bank_lo <= 0;
bank_hi <= 0;
IOE_ena <= 0;
IOF_ena <= 0;
IOE_wr_ena <= 0;
IOF_wr_ena <= 0;
IOE_bank <= 0;
IOF_bank <= 0;
if(~init_n) begin
exrom_overide <= 0;
game_overide <= 1;
reu_map <= 0;
allow_bank <= 0;
clock_port <= 0;
end
end
else if(cart_disable) begin
exrom_overide <= 1;
game_overide <= 1;
IOE_wr_ena <= 0;
IOF_wr_ena <= 0;
IOE_ena <= 0;
IOF_ena <= 0;
romL_we <= 0;
allow_freeze <= 1;
end else begin
if(ioe_wr & !addr_in[7:1]) begin
bank_hi <= {data_in[7],data_in[4:3]};
if(~addr_in[0]) begin
cart_disable <= data_in[2];
end
else begin
if(data_in[6]) reu_map <= 1;
if(data_in[1]) allow_bank <= 1;
clock_port <= data_in[0];
end
if((data_in[6] | allow_freeze) & ~addr_in[0]) begin
allow_freeze <= 1;
game_overide <= ~data_in[0];
exrom_overide <= data_in[1];
romL_we <= data_in[5];
end
end
end
end
If you want to test, here's a build with the this patch (modified a bit). c64_230226.zip
This one works great!
I've just tested the more common RR based cartridge images and they work without any flaws as far as i can tell.
Tested ones:
On the 3.8q i've also tested TASS which holds it's sourcecode in cartridge RAM and assembles from there. Works too:
Nice, a built-in assembler. One note that REU compatibility is currently useless, as REU is disabled if a cartridge is loaded (not all carts are REU-compatible).
RR cartridges are the successor to the Action Replay ones which have increased ROM (up to 128 KiB) and RAM (32 KiB). Would it be possible to support those cartridges or are the FPGAs resources to constrained?
Attached a CRT file of RR 3.8 rr38p-tmp12.zip