About Digital CiM framework evaluation

[0x7D6E7FD]

Hello Tanner,

This is not exactly an issue. I have a few questions as I have recently started to explore the framework.

1. Does this framework can evaluate all kind of Fully Digital CiM framework ?
2. If yes then how can I make the YAML file to evaluate that ?

Thanks !

[tanner-andrulis]

Thank you for the question. I am afraid I can not answer without more specific information. What exactly would you like to model?

[0x7D6E7FD]

Hello, Yes. I am trying to evaluate a fully digital framework where I have 8T latch as memory cell and Wallace tree as component. If this is possible , Can you please point me out where should I look at to specify this components ?

[tanner-andrulis]

The workspace/README file references tutorials that you should complete. After completing those tutorials, look through the different notebooks in workspace/models/arch/1_macro/*. The Colonnade architecture is an example of a digital CiM macro if you'd like to use it as a reference. The workspace/models/memory_cells directory includes memory cells if you'd like to implement the 8T latch.

[0x7D6E7FD]

Thanks, I was trying to debug to understand the calculations behind the scene. In one Issue I saw you mentioned to look into the parsed-processed-input.yaml file. what does this file capture ? I was checking this file for different architecture and found out each dac_x2x_ladder component is in each file. But I thought that this element only should be in wang_vlsi_2022 architecture. I found this element in the colonnade architecture's parsed-processed-input.yaml file as well. Can you please let me know what is the easier way to debug or understand which component to use for which architecture ?

• !Component # Model the digital logic input ports here, rather than in the CIM logic,

  because each time a row is asserted, it sends its input to ALL input

         # ports on that row.

  name: digital_logic_input_ports <<<: [component_defaults, keep_inputs, no_coalesce] subclass: colonnade_cim_logic_input_port attributes: width: DAC_RESOLUTION n_instances: column.get_fanout() switching_activity: (AVERAGE_INPUT_VALUE (1 - AVERAGE_INPUT_VALUE)) ** 0.5 voltage: VOLTAGE

  also while designing a new component how do I know which attributes to add ?

[tanner-andrulis]

The parsed-processed-input.yaml file gathers all input files into one place, including substituted & parsed variables. As part of this file, it gathers all components into one components list. Note that this does NOT mean that the components are necessarily used in the architecture; only that they are present in the input files. To see what components are actually used in the architecture, look at the timeloop-mapper.accelergy.log file in the same directory. You can also run "accelergy -v parsed-processed-input.yaml" to see what plug-ins are called to model each component.

To understand what attributes to add, I will refer you to the exercises in the exercises repository on using Accelergy (https://github.com/Accelergy-Project/timeloop-accelergy-exercises). After completing these tutorials, you can look at any of the following:

• The Accelergy output from calling "accelergy -v" on your parsed-processed-input file.
• Call accelergy --list to list components
• Look at the plug-ins individually to see the arguments they expect
• Look at the compound components defined in the components directory to see what arguments they expect