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mit-ll / CEP

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
BSD 2-Clause "Simplified" License
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Simulation compiler throwing error #5

Closed Rahul-Kande closed 4 years ago

Rahul-Kande commented 4 years ago

Hello,

I am trying to add my custom bare-metal test to cosim. But, if I use asm instructions in my test function, the 'make' command is throwing the following error.

$ make
/usr/bin/g++ -DUSE_DPI -I /home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/pli -I /home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/include -I /home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/s
hare -I /home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/simDiag  -I /home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/drivers/diag  -I /home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/drivers/
cep_tests -I /home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/include -g -Wno-format -Wno-narrowing -D_SIM_SW_ENV -DSIM_ENV_ONLY -c -o /home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/drivers/diag/
mytest.obj /home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/drivers/diag/mytest.cc
/home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/drivers/diag/mytest.cc: Assembler messages:
/home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/drivers/diag/mytest.cc:101: Error: no such instruction: `addi x0,x0,0'
/home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/drivers/diag/mytest.cc:102: Error: no such instruction: `addi x0,x0,0'
/home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/drivers/diag/mytest.cc:103: Error: no such instruction: `addi x0,x0,0'
/home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/drivers/diag/mytest.cc:104: Error: no such instruction: `addi x0,x0,0'
make: *** [/home/grads/r/rahulkande/thesis/rocket_core/CEP/cosim/drivers/diag/mytest.obj] Error 1

I think it is trying to compile my test function with the x86 g++ instead of riscv-g++ and hence is not able to recognize the riscv asm instructions. I don't understand why the test has to be compiled with the x86 g++. Is there a way I can bypass this and compile only with riscv-g++ ?

Please help me resolve the issue.

Thanking you in advance

bchetwynd commented 4 years ago

@Rahul-Kande :

Did you setup the RISC-V toolchain per the instructions in the README.md file? Including setting of the RISCV environment variable...

Our co-simulation environment (v2.3) currently assumes that the RISCV toolchain is installed in /opt/RISCV... so I would put it there for now.

Rahul-Kande commented 4 years ago

Yes, I did. I dont think that is the issue. Because, if I write a normal C program in my test function, it runs successfully. It only throws an error when I have asm instructions in the test function.

bchetwynd commented 4 years ago

For RISC-V inline assembly, surround your code with the following:

ifdef BARE_MODE

asm volatile ("addi x0, x0, 0");

endif

Otherwise, the cosim build process will try to compile the code for both BFM and baremetal modes which are x86 and RISC-V respectively. If the assembly isn't valid for BOTH instruction sets, you'll have an issue. The valid mode defines are: BARE_MODE LINUX_MODE BFM_MODE

Rahul-Kande commented 4 years ago

that worked!

Thank you very much :)