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mit-pdos / xv6-riscv

Xv6 for RISC-V
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Fix boot on newer qemu #62

Open lf- opened 3 years ago

lf- commented 3 years ago

We were previously noncompliant with the RISC-V specification, and so was qemu: if there are no PMP registers configured, according to the spec, any access to memory, including instruction fetch, from S- or U- mode, should fail (see section 3.6.1 of the RISC-V privileged spec).

However, qemu was not enforcing this properly prior to https://github.com/qemu/qemu/commit/d102f19a208. Running a qemu newer than this would get stuck in an infinite loop hitting the exception vector repeatedly.

This commit adds trivial support for the PMP registers, writing a value such that all accesses from S- and U- mode have their access managed solely by the page tables. This restores the previous behaviour.

Further, it makes the machine mode timer vector check if it receives an unexpected interrupt if so, jump to a specific infinite loop. This should make any potential future occurrences of interrupt issues more obvious.

I found this bug when my own kernel (https://github.com/lf-/mu) didn't boot, and after a "fun" session with a gdb attached to qemu, I found this issue and wondered if xv6 had the same bug. Turns out it did.

Fix #76.

ceciivanov commented 2 years ago

We were previously noncompliant with the RISC-V specification, and so was qemu: if there are no PMP registers configured, according to the spec, any access to memory, including instruction fetch, from S- or U- mode, should fail (see section 3.6.1 of the RISC-V privileged spec).

However, qemu was not enforcing this properly prior to qemu/qemu@d102f19. Running a qemu newer than this would get stuck in an infinite loop hitting the exception vector repeatedly.

This commit adds trivial support for the PMP registers, writing a value such that all accesses from S- and U- mode have their access managed solely by the page tables. This restores the previous behaviour.

Further, it makes the machine mode timer vector check if it receives an unexpected interrupt if so, jump to a specific infinite loop. This should make any potential future occurrences of interrupt issues more obvious.

I found this bug when my own kernel (https://github.com/lf-/mu) didn't boot, and after a "fun" session with a gdb attached to qemu, I found this issue and wondered if xv6 had the same bug. Turns out it did.

Fix #76.

hello can I ask how I can pull that change so I can fix the boot bug?

lf- commented 2 years ago

hello can I ask how I can pull that change so I can fix the boot bug?

git fetch origin pull/62/head
git merge FETCH_HEAD

where you replace origin with whatever your remote for the upstream xv6 repository is (i.e. the one pointing to https://github.com/mit-pdos/xv6-riscv).