This is a bit difficult to investigate since from working or failing gateware (same verilog/same ucf) we just see slight differences in the P&R results.
The best to get consecutive builds working each time is probably to add some location constraints on the design for the DRAM controller. Not sure this will totally fix the problem (wich is probably related to a missing timing constraint...), but this will increase probablity to have working builds.
This is a bit difficult to investigate since from working or failing gateware (same verilog/same ucf) we just see slight differences in the P&R results.
The best to get consecutive builds working each time is probably to add some location constraints on the design for the DRAM controller. Not sure this will totally fix the problem (wich is probably related to a missing timing constraint...), but this will increase probablity to have working builds.