Create test base class for multi-clock-domain unittests

mithro / valentyusb

USB Full-Speed core written in migen/LiteX

BSD 3-Clause "New" or "Revised" License

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Create test base class for multi-clock-domain unittests #13

Open mithro opened 5 years ago

mithro commented 5 years ago

A bunch of the tests have to deal with sys, usb_12 and usb_48 clock domains. It would good if there was a common unittest base class which dealt with a lot of the complexity around these multiple clock domains for you.