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mithro / valentyusb

USB Full-Speed core written in migen/LiteX
BSD 3-Clause "New" or "Revised" License
17 stars 3 forks source link

Finish writing the per endpoint FIFO CPU interface #5

Open mithro opened 5 years ago

mithro commented 5 years ago

This is the one which worked on the TinyFPGA-BX with tinyusb.

See https://github.com/mithro/valentyusb/blob/usb12/valentyusb/old_usbcore.py#L954-L1037

mithro commented 5 years ago

https://github.com/mithro/valentyusb/blob/493ab024423a1368bc34fee735460a1ee9ba945a/valentyusb/old_usbcore.py#L954-L1037