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Allow memory barriers on a non-intel arches #102

Closed GoogleCodeExporter closed 9 years ago

GoogleCodeExporter commented 9 years ago 
In fact memory barriers are available on a many other architectures than only 
on a intel one. Let's allow leveldb to build on them.

Original issue reported on code.google.com by lemenkov on 11 Jul 2012 at 11:05

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GoogleCodeExporter commented 9 years ago 
As far as I can tell, you changed:
   #elif defined(ARCH_CPU_X86_FAMILY) && defined(__GNUC__)
   inline void MemoryBarrier() {
     __asm__ __volatile__("" : : : "memory");
   }
to:
   #elif defined(__GNUC__)
   inline void MemoryBarrier() {
     __asm__ __volatile__("" : : : "memory");
   }

But I don't believe that's correct. The __asm__ statement only takes care of
compiler induced reordering. On many architectures (the classic example is
an alpha), the hardware can also reorder memory accesses.  x86 does less
reordering and that's why this definition of MemoryBarrier() was guarded
by a check for x86.

Original comment by san...@google.com on 11 Jul 2012 at 3:39