Open eehsx opened 9 months ago
Thanks Markus for your files.
SSD1309 needs "U8X8_CA(c0,a0)" command that generates this sequence : CS low, DC low, send 1 byte C0, send 1 byte A0, CS high
Your design includes CS management by spi ESP IDF : spi_device_interface_config_t dev_config; ... dev_config.spics_io_num = u8g2_esp32_hal.bus.spi.cs;
So, I get : DC low, CS low, send 1 byte C0, CS high, CS low, send 1 byte A0, CS high. And it's not working.
So I removed CS management by spi ESP IDF driver : dev_config.spics_io_num = U8G2_ESP32_HAL_UNDEFINED; Then I add to u8g2_esp32_spi_byte_cb function :
case U8X8_MSG_CAD_START_TRANSFER: if (u8g2_esp32_hal.bus.spi.cs != U8G2_ESP32_HAL_UNDEFINED) { gpio_set_level(u8g2_esp32_hal.bus.spi.cs, 0); } //ESP_LOGI(TAG, "U8X8_MSG_CAD_START_TRANSFER done."); break; case U8X8_MSG_CAD_END_TRANSFER: if (u8g2_esp32_hal.bus.spi.cs != U8G2_ESP32_HAL_UNDEFINED) { gpio_set_level(u8g2_esp32_hal.bus.spi.cs, 1); } //ESP_LOGI(TAG, "U8X8_MSG_CAD_END_TRANSFER done."); break;
So now, CS is controled by u8g2 driver and it works.
I hope this can help.
Thanks Markus for your files.
SSD1309 needs "U8X8_CA(c0,a0)" command that generates this sequence : CS low, DC low, send 1 byte C0, send 1 byte A0, CS high
Your design includes CS management by spi ESP IDF : spi_device_interface_config_t dev_config; ... dev_config.spics_io_num = u8g2_esp32_hal.bus.spi.cs;
So, I get : DC low, CS low, send 1 byte C0, CS high, CS low, send 1 byte A0, CS high. And it's not working.
So I removed CS management by spi ESP IDF driver : dev_config.spics_io_num = U8G2_ESP32_HAL_UNDEFINED; Then I add to u8g2_esp32_spi_byte_cb function :
So now, CS is controled by u8g2 driver and it works.
I hope this can help.