[dfg] Fix STM32F7 DTCM sizes

[salkinium]

Fixes #53.

cc @mikewolfram

You can do this in the modm submodule to test this:

git remote add salkinium https://github.com/salkinium/modm-devices.git
git fetch
git checkout salkinium/fix/stm32f7_dtcm

[mikewolfram]

Except the extra start it looks like mine.

Maybe also add the ITCM Flash address and size while looking into it?

[salkinium]

Maybe also add the ITCM Flash address and size while looking into it?

What do you mean? Is this incorrect? <memory name="itcm" access="rwx" start="0x00" size="16384"/>

[mikewolfram]

This is the instruction RAM. But the M7 can access the Flash via 2 different buses: AXIM and ITCM. For AXIM the flash address is 0x0800 0000, but for ITCM access it is 0x0020 0000 (if I remember correctly). So there are two ways to read/execute from flash.

BTW: ART is enabled, but is only used when flash is accessed via ITCM.

[salkinium]

Ah, I think I understand:

• instr. and data can be placed into flash at 0x0020'0000, then they go through the ST's ART accelerator via ITCM bus.
• instr. and data can be placed into flash at 0x0800'0000, then they got through the Cortex-M7's I-/D-Cache via AXIM interface.

It's unclear to me what is faster? The Cortex-M7 caches are larger than the ART accelerator (at least 4kB for caches, vs 2kB for ART), perhaps a split approach (inst. via ITCM, data via AXIM) is best to get 2x parallel 64-bit access?

[salkinium]

I could add a flash alias to 0x0020'0000, but I think this is more of a linkerscript feature, than a modm-devices feature? In any cases doing this right requires changes to the linkerscripts and memory preparation in the modm:platform:core module for STM32.

[salkinium]

The embedded flash has three main interfaces:

• 64-bits ITCM interface:
  • It is connected to the ITCM bus of Cortex-M7 and used for instruction execution and data read access.
  • Write accesses are not supported on ITCM interface
  • Supports a unified 64 cache lines of 256 bits (ART accelerator)
• 64-bits AHB interface:
  • It is connected to the AXI bus of Cortex-M7 through the AHB bus matrix and used for code execution, read and write accesses.
  • DMAs and peripherals DMAs data transfer on Flash are done through the AHB interface whatever the addressed flash interface TCM or AHB.
• 32-bits AHB register interface:
  • It is used for control and status register accesses.

[salkinium]

So DMA always goes through AHB, so I guess it would be better to have the CPU-bound accesses done via the ITCM bus?

[mikewolfram]

I saw a table of speed comparison, but can't find it right now. At the end, the speed is comparable. But since the ITCM is directly connected to the core and not going thought the AHB it might make the system more efficient?

Anyway, yes, ITCM flash requires special linker file, not sure how to create one. Maybe option in the XML? I was trying to prepare one but failed. The STM32 isn't starting at all, not even the reset handler is called. Break points couldn't be set. I wanted to see if there's maybe a limitation to debug through ITCM?

My ideas was simply, if the devices part is changed, maybe simply add the ITCM flash, maybe later it could be useful.

[salkinium]

Maybe option in the XML?

No, I'd leave the XML as is, also the Flash address at 0x0800'0000, since this is consistent with the rest of the devices.

I would then rework the :platform:core module to simply move Flash to 0x0020'0000. I have a STM32F7 and a bit of time, I'll open a PR with that idea.

[mikewolfram]

I have a STM32F7 and a bit of time, I'll open a PR with that idea.

👍